View MB96F356YSBPMC-GSE2_3756558.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

preliminary fme-mb96350 rev 5 fujitsu semiconductor data sheet 2008-2-4 16-bit proprietary microcontroller cmos f 2 mc-16fx mb96350 series mb96f356 description mb96350 series is based on fujitsus advanced 16fx architecture (16-bit with instruction pipeline for risc-like performance). the cpu uses the same instruction set as the established 16lx series - thus allowing for easy migration of 16lx software to the new 16fx products. 16fx improvements compared to the previous generation include signi?antly improved performance - even at the same operation frequency, reduced power consumption and faster start-up time. for highest processing speed at optimized power consumption an internal pll can be selected to supply the cpu with up to 56mhz operation frequency from an external 4mhz resonator. the result is a minimum instruction cycle time of 17.8ns going together with excellent emi behavior. an on-chip clock modulation circuit signi?antly reduces emission peaks in the frequency spectrum. the emitted power is minimized by the on-chip voltage regulator that reduces the internal cpu voltage. a ?xible clock tree allows to select suitable operation frequencies for peripheral resources independent of the cpu speed.
preliminary mb96350 series fme-mb96350 rev 5 2 2008-2-4
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 3 features feature description technology 0.18 m cmos cpu f2mc-16fx cpu up to 56 mhz internal, 17.8 ns instruction cycle time optimized instruction set for controller applications (bit, byte, word and long-word data types; 23 different addressing modes; barrel shift; variety of pointers) 8-byte instruction execution queue signed multiply (16-bit 16-bit) and divide (32-bit/16-bit) instructions available system clock on-chip pll clock multiplier (x1..25, x1 when pll stop) 3-16 mhz external quartz clock up to 56 mhz external clock 32-100 khz subsystem quartz clock 100khz/2mhz internal rc clock for quick and safe startup, oscillator stop detection, watchdog clock source selectable from main- and subclock oscillator (part number suffix ?? and on-chip rc oscillator, independently for cpu and 2 clock domains of peripherals. low power consumption - 13 operating modes : (different run, sleep, timer modes, stop mode) clock modulator on-chip voltage regula- tor internal voltage regulator supports reduced internal mcu voltage, offering low emi and low power consumption figures low voltage reset reset is generated when supply voltage is below minimum. code security protects rom content from unintended read-out memory patch function replaces rom content can also be used to implement embedded debug support dma automatic transfer function independent of cpu, can be assigned freely to resources interrupts fast interrupt processing 8 programmable priority levels non-maskable interrupt (nmi) timers three independent clock timers (23-bit rc clock timer, 23-bit main clock timer, 17-bit sub clock timer) watchdog timer
preliminary mb96350 series fme-mb96350 rev 5 4 2008-2-4 can supports can protocol version 2.0 part a and b iso16845 certified bit rates up to 1 mbit/s 32 message objects each message object has its own identifier mask programmable fifo mode (concatenation of message objects) maskable interrupt disabled automatic retransmission mode for time triggered can applications programmable loop-back mode for self-test operation usart full duplex usarts (sci/lin) wide range of baud rate settings using a dedicated reload timer special synchronous options for adapting to different synchronous serial protocols lin functionality working either as master or slave lin device i2c up to 400 kbit/s master and slave functionality, 8-bit and 10-bit addressing a/d converter sar-type 10-bit resolution signals interrupt on conversion end, single conversion mode, continuous conversion mode, stop conversion mode, activation by software, external trigger or reload timer reload timers 16-bit wide prescaler with 1/2 1 , 1/2 2 , 1/2 3 , 1/2 4 , 1/2 5 , 1/2 6 of peripheral clock frequency event count function free running timers signals an interrupt on overflow, supports timer clear upon match with output compare (0, 4), prescaler with 1, 1/2 1 , 1/2 2 , 1/2 3 , 1/2 4 , 1/2 5 , 1/2 6 , 1/2 7 ,1/2 8 of peripheral clock frequency input capture units 16-bit wide signals an interrupt upon external event rising edge, falling edge or rising & falling edge sensitive output compare units 16-bit wide signals an interrupt when a match with 16-bit i/o timer occurs a pair of compare registers can be used to generate an output signal. programmable pulse generator 16-bit down counter, cycle and duty setting registers interrupt at trigger, counter borrow and/or duty match pwm operation and one-shot operation internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral clock as counter clock and reload timer overflow as clock input can be triggered by software or reload timer feature description
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 5 real time clock can be clocked either from sub oscillator (devices with part number suffix ??, main oscillator or from the rc oscillator facility to correct oscillation deviation of sub clock or rc oscillator clock (clock calibration) read/write accessible second/minute/hour registers can signal interrupts every half second/second/minute/hour/day internal clock divider and prescaler provide exact 1s clock external interrupts edge sensitive or level sensitive interrupt mask and pending bit per channel each available can channel rx has an external interrupt for wake-up selected usart channels sin have an external interrupt for wake-up non maskable interrupt disabled after reset once enabled, can not be disabled other than by reset. level high or level low sensitive pin shared with external interrupt 0. external bus interface 8-bit or 16-bit bidirectional data up to 24-bit addresses 6 chip select signals multiplexed address/data lines wait state request external bus master possible timing programmable i/o ports virtually all external pins can be used as general purpose i/o all push-pull outputs (except when used as i2c sda/scl line) bit-wise programmable as input/output or peripheral signal bit-wise programmable input enable bit-wise programmable input levels (automotive / cmos-schmitt trigger / ttl) bit-wise programmable pull-up resistor bit-wise programmable output driving strength for emi optimization packages 64-pin plastic lqfp m23/m24 feature description
preliminary mb96350 series fme-mb96350 rev 5 6 2008-2-4 flash memory supports automatic programming, embedded algorithm tm*1 write/erase/erase-suspend/resume commands a flag indicating completion of the algorithm number of erase cycles: 10,000 times data retention time: 20 years erase can be performed on each sector individually sector protection flash security feature to protect the content of the flash low voltage detection during flash erase *1 : embedded algorithm is a trade mark of advanced micro devices inc. feature description
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 7 product lineup features mb96v300b mb9635x product type evaluation sample flash product: mb96f35x mask rom product: mb9635x product options ys na lvd persistently on / single clock devices rs lvd can be disabled / single clock devices yw lvd persistently on / dual clock devices rw lvd can be disabled / dual clock devices flash/ rom ram 288kb 12kb rom/flash memory emulation by external ram, 92kb internal ram mb96f356r, mb96f356y package bga416 fpt-64p-m23/24 dma 16 channels 4 channels usart 10 channels 4 channels i2c 2 channels 1 channel a/d converter 40 channels 15 channels a/d converter reference voltage switch yes no 16-bit reload timer 6 channels + 1 channel (for ppg) 4 channels + 1 channel (for ppg) 16-bit free-running timer 4 channels 2 channels 16-bit output compare 12 channels 4 channels 16-bit input capture 12 channels 6 channels 16-bit programmable pulse generator 20 channels 20 channels can interface 5 channels 2 channels external interrupts 16 channels 13 channels non-maskable interrupt 1 channel real time clock 1 i/o ports 136 49 for part number with suf? "w", 51 for part number with suf? "s" external bus interface yes
preliminary mb96350 series fme-mb96350 rev 5 8 2008-2-4 chip select 6 signals clock output function 2 channels low voltage reset yes on-chip rc-oscillator yes features mb96v300b mb9635x
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 9 block diagram block diagram of mb96(f)35x i2c 1 ch. sda0 scl0 dma controller boot rom peripheral bus bridge peripheral bus bridge 16fx core bus (clkb) usart 4 ch. 10-bit adc 15 ch. i/o timer 0 icu 0/1 can interface 2 ch. real time clock watchdog ram voltage regulator sin2, sin2_r, sin3, sin7_r, sin8_r sot2, sot2_r, sot3, sot7_r, sot8_r sck2, sck2_r, sck3, sck7_r, sck8_r wot av cc av ss avrh an0 ... an14 adtg_r frck0 in0 ... in1 out4 ... out7 tx1, tx2 rx1, rx2 peripheral bus 1 (clkp1) peripheral bus 2 (clkp2) v cc v ss c i/o timer 1 icu 4/5/6/7 frck1 in4 ... in7 16fx cpu interrupt controller clock & mode controller flash memory a memory patch unit ad00 ... ad15 a16 ... a21 ale rdx wr(l)x, wrhx hrq hakx rdy eclk external bus interface cs0_r ... cs5_r nmi_r ocu 4/5/6/7 16-bit reload timer 4 ch. tin0_r, tin2_r tin1, tin3 tot0_r, tot2_r tot1, tot3 external interrupt int8 ... int15 int0_r, int2_r, int4_r int3_r1 int7_r, int9_r ... int11_r 16-bit ppg 20 ch. ppg0 ... ppg7, ppg12 ... ppg15 ttg0, ttg1, ttg4 ... ttg9, ttg12 ... ttg15 ppg8_r ... ppg11_r, ppg16_r ... ppg19_r ttg8_r ... ttg11_r, ttg16_r ... ttg19_r ckot0_r, ckot1, ckot1_r ckotx1 x0, x1 x0a, x1a 1) rstx md0...md2 rlt6 1) x0a/x1a only available on devices with suf? ?
preliminary mb96350 series fme-mb96350 rev 5 10 2008-2-4
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 11 pin assignments pin assignment of mb96(f)35x remark: mb96(f)35x products are pin-compatible to f 2 mc-16lx family mb90350 series. lqfp - 64 package code (mold) fpt-64p-m23/m24 (fpt-64p-m23/m24) p00_1/ad01/int9/sot7_r/ttg9_r p00_2/ad02/int10/sin7_r/ttg10_r p00_3/ad03/int11/sck8_r/ttg11_r p00_4/ad04/int12/sot8_r/ppg8_r p00_5/ad05/int13/sin8_r/ppg9_r p00_6/ad06/int14/ppg10_r p00_7/ad07/int15/ppg11_r p01_0/ad08/ckot1/tin1/ttg16_r p01_1/ad09/ckotx1/tot1/ttg17_r p01_2/ad10/int11_r/sin3/ttg18_r p01_3/ad11/sot3/ttg19_r p01_4/ad12/sck3/ppg16_r p01_5/ad13/sin2_r/int7_r/ppg17_r p01_6/ad14/sot2_r/ppg18_r p01_7/ad15/sck2_r/ppg19_r p02_0/a16/ppg12/ckot1_r p02_1/a17/ppg13 p02_2/a18/ppg14/ckot0_r p02_3/a19/ppg15 p02_4/a20/ttg8/ttg0/in0 p02_5/a21/ttg9/ttg1/in1/adtg_r vcc vss x1 x0 md1 md2 p06_7/an7/ppg7 p06_6/an6/ppg6 p06_5/an5/ppg5/cs5_r p06_4/an4/ppg4/cs4_r p06_3/an3/ppg3/cs3_r p06_2/an2/ppg2/cs2_r p06_1/an1/ppg1/cs1_r p06_0/an0/ppg0/cs0_r avss avrh avcc p05_6/an14/int4_r p05_5/an13/int0_r/nmi_r p05_4/an12/tot3/int2_r p00_0/ad00/int8/sck7_r/ttg8_r rstx md0 p03_0/ale/in4/ttg4/ttg12/tot0_r p03_1/rdx/in5/ttg5/ttg13/tot2_r p03_2/wr(l)x/rx2/int10_r p03_3/tx2/wrhx p03_4/hrq/out4 p03_5/hakx/out5 p03_6/rdy/out6 p03_7/eclk/out7 x0a/p04_0 1) x1a/p04_1 1) vss c p04_2/in6/rx1/int9_r/ttg6/ttg14 p04_3/in7/tx1/ttg7/ttg15 p04_4/sda0/frck0/tin0_r p04_5/scl0/frck1/tin2_r p05_0/an8/sin2/int3_r1 p05_1/an9/sot2 p05_2/an10/sck2 p05_3/an11/tin3/wot 89 12345 7 6 10111213141516 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 devices with suf? w: x0a/x1a devices with suf? s: p04_0, p04_1 1)
preliminary mb96350 series fme-mb96350 rev 5 12 2008-2-4
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 13 pin function description pin function description (1 / 2) pin name feature description adn external bus external bus interface (multiplexed mode) address output and data input/output adtg_r adc relocated a/d converter trigger input ale external bus external bus address latch enable output an external bus external bus address output ann adc a/d converter channel n input av cc supply analog circuits power supply avrh adc a/d converter high reference voltage input av ss supply analog circuits power supply c voltage regulator internally regulated power supply stabilization capacitor pin ckotn clock output function clock output function n output ckotn_r clock output function relocated clock output function n output ckotxn clock output function clock output function n inverted output eclk external bus external bus clock output csn external bus external bus chip select n output frckn free running timer free running timer n input hakx external bus external bus hold acknowledge hrq external bus external bus hold request inn icu input capture unit n input intn external interrupt external interrupt n input intn_r external interrupt relocated external interrupt n input mdn core input pins for specifying the operating mode. nmi_r external interrupt relocated non-maskable interrupt input outn ocu output compare unit n waveform output pxx_n gpio general purpose io ppgn ppg programmable pulse generator n output ppgn_r ppg relocated programmable pulse generator n output rdx external bus external bus interface read strobe output rdy external bus external bus interface external wait state request input
preliminary mb96350 series fme-mb96350 rev 5 14 2008-2-4 rstx core reset input rxn can can interface n rx input sckn usart usart n serial clock input/output sckn_r usart relocated usart n serial clock input/output scln i2c i2c interface n clock i/o input/output sdan i2c i2c interface n serial data i/o input/output sinn usart usart n serial data input sinn_r usart relocated usart n serial data input sotn usart usart n serial data output sotn_r usart relocated usart n serial data output tinn reload timer reload timer n event input tinn_r reload timer relocated reload timer n event input totn reload timer reload timer n output totn_r reload timer relocated reload timer n output ttgn ppg programmable pulse generator n trigger input ttgn_r ppg relocated programmable pulse generator n trigger input txn can can interface n tx output v cc supply power supply v ss supply power supply wot rtc real timer clock output wrhx external bus external bus high byte write strobe output wrlx/wrx external bus external bus low byte / word write strobe output x0 clock oscillator input x0a clock subclock oscillator input (only for devices with suf? "w") x1 clock oscillator output x1a clock subclock oscillator output (only for devices with suf? "w") pin function description (2 / 2) pin name feature description
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 15 pin circuit type fpt-64p-m23/24 pin no. circuit type 1 supply 2g 3 to 15 i 16,17 h 18 supply 19,20 b 1) 19,20 h 2) 21 to 23 c 24 to 44 h 45 e 46,47 a 48,49 supply 50 f 51 h 52,53 n 54 to 61 h 62,63 i 64 supply 1) devices with suf? ? 2) devices without suf? ?
preliminary mb96350 series fme-mb96350 rev 5 16 2008-2-4 i/o circuit type type circuit remarks a high-speed oscillation circuit: programmable between oscillation mode (ex- ternal crystal or resonator connected to x0/x1 pins) and fast external clock input (fci) mode (external clock connected to x0 pin) programmable feedback resistor = approx. 2 * 0.5 m ? . feedback resistor is grounded in the center when the oscillator is disabled or in fci mode b low-speed oscillation circuit: programmable feedback resistor = approx. 2*5m ? . feedback resistor is grounded in the center when the oscillator is disabled c mask rom and eva device: cmos hysteresis input pin flash device: cmos input pin e cmos hysteresis input pin pull-up resistor value: approx. 50 k ? x1 x0 r r mrfbe xout fci 0 1 fci or osc disable x1a x0a r r srfbe xout osc disable r hysteresis inputs r pull-up resistor hysteresis inputs
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 17 f power supply input protection circuit g a/d converter ref+ (avrh) power supply input pin with protection circuit flash devices do not have a protection circuit against vcc for pin avrh h cmos level output (programmable i ol =5ma, i oh = -5ma and i ol = 2ma, i oh = -2ma) 2 different cmos hysteresis inputs with input shutdown function automotive input with input shutdown function ttl input with input shutdown function programmable pull-up resistor: 50k ? approx. type circuit remarks ane avr ane pout pull-up control nout r hysteresis input automotive input ttl input hysteresis input standby control for input shutdown standby control for input shutdown standby control for input shutdown standby control for input shutdown
preliminary mb96350 series fme-mb96350 rev 5 18 2008-2-4 i cmos level output (programmable i ol =5ma, i oh = -5ma and i ol = 2ma, i oh = -2ma) 2 different cmos hysteresis inputs with input shutdown function automotive input with input shutdown function ttl input with input shutdown function. programmable pull-up resistor: 50k ? approx. analog input n cmos level output (i ol = 3ma, i oh = -3ma) 2 different cmos hysteresis inputs with input shutdown function automotive input with input shutdown function ttl input with input shutdown function programmable pull-up resistor: 50k ? approx. type circuit remarks r hysteresis input hysteresis input standby control for input shutdown standby control for input shutdown standby control for input shutdown standby control for input shutdown pull-up control pout nout automotive input ttl input analog input pout pull-up control nout r hysteresis input automotive input ttl input hysteresis input standby control for input shutdown standby control for input shutdown standby control for input shutdown standby control for input shutdown
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 19 memory map mb96v300b mb96(f)3xx ff:ffff h emulation rom user rom / external bus *4 de:0000 h external bus external bus 10:0000 h 0f:e000 h boot-rom boot-rom reserved reserved 0e:0000 h external ram 02:0000 h internal ram bank 1 reserved ramend1 *2 internal ram bank 1 ram availability de- pending on the device ramstart1 2 01:0000 h reserved rom/ram mirror rom/ram mirror 00:8000 h internal ram bank 0 internal ram bank 0 ramstart0 *2 reserved ramstart0 *3 external bus external bus end address *2 00:0c00 h external bus peripherals peripherals 00:0380 h 00:0180 h gpr *1 gpr *1 00:0100 h dma dma 00:00f0 h external bus external bus 00:0000 h peripheral peripheral *1: unused gpr banks can be used as ram area *2: for external bus end address and ramstart/end addresses, please refer to the table on the next page. *3: for eva device, ramstart0 depends on the con?uration of the emulated device. *4: for details about user rom area, see the user rom memory map on the following pages. the external bus area and dma area are only available if the device contains the corresponding resource. the available ram and rom area depends on the device.
preliminary mb96350 series fme-mb96350 rev 5 20 2008-2-4 ramstart/end and external bus end addresses devices bank 0 ram size bank 1 ram size external bus end address ramstart0 ramstart1 ramend1 mb96f356 12kb - 00:51ff h 00:5240 h --
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 21 user rom memory map for flash devices mb96f356 alternative mode cpu address flash memory mode address flash size 288kbyte ff:ffff h ff:0000 h 3f:ffff h 3f:0000 h s39 - 64k flash a fe:ffff h fe:0000 h 3e:ffff h 3e:0000 h s38 - 64k fd:ffff h fd:0000 h 3d:ffff h 3d:0000 h s37 - 64k fc:ffff h fc:0000 h 3c:ffff h 3c:0000 h s36 - 64k fb:ffff h fb:0000 h 3b:ffff h 3b:0000 h external bus fa:ffff h fa:0000 h 3a:ffff h 3a:0000 h f9:ffff h f9:0000 h 39:ffff h 39:0000 h f8:ffff h f8:0000 h 38:ffff h 38:0000 h f7:ffff h f7:0000 h 37:ffff h 37:0000 h f6:ffff h f6:0000 h 36:ffff h 36:0000 h f5:ffff h f5:0000 h 35:ffff h 35:0000 h f4:ffff h f4:0000 h 34:ffff h 34:0000 h f3:ffff h f3:0000 h 33:ffff h 33:0000 h f2:ffff h f2:0000 h 32:ffff h 32:0000 h f1:ffff h f1:0000 h 31:ffff h 31:0000 h f0:ffff h f0:0000 h 30:ffff h 30:0000 h e0:ffff h e0:0000 h df:ffff h df:8000 h reserved df:7fff h df:6000 h 1f:7fff h 1f:6000 h sa3 - 8k flash a df:5fff h df:4000 h 1f:5fff h 1f:4000 h sa2 - 8k df:3fff h df:2000 h 1f:3fff h 1f:2000 h sa1 - 8k df:1fff h df:0000 h 1f:1fff h 1f:0000 h sa0 - 8k *1 de:ffff h de:0000 h reserved *1: sector sa0 contains the rom con?uration block rcba at cpu address df:0000 h - df:007f h
preliminary mb96350 series fme-mb96350 rev 5 22 2008-2-4 serial programming communication interface note: for handshaking pin, please use for this device the default port p00_1 on pin 25. if any other pin is required, please contact the flash programmer device vendor. usart pins for flash serial programming (md[2:0] = 010) mb96f35x pin number usart number normal function lqfp-64 9 usart2 sin2 10 sot2 11 sck2 34 usart3 sin3 35 sot3 36 sck3 26 usart7 sin7_r 25 sot7_r 24 sck7_r 29 usart8 sin8_r 28 sot8_r 27 sck8_r
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 23 i/o map i/o map mb96(f)35x (1 / 27) address register abbreviation 8-bit access abbreviation 16-bit access access 000000h i/o port p00 - port data register pdr00 rw 000001h i/o port p01 - port data register pdr01 rw 000002h i/o port p02 - port data register pdr02 rw 000003h i/o port p03 - port data register pdr03 rw 000004h i/o port p04 - port data register pdr04 rw 000005h i/o port p05 - port data register pdr05 rw 000006h i/o port p06 - port data register pdr06 rw 000007h- 000017h reserved - 000018h adc0 - control status register low adcsl adcs rw 000019h adc0 - control status register high adcsh rw 00001ah adc0 - data register low adcrl adcr r 00001bh adc0 - data register high adcrh r 00001ch adc0 - setting register adsr rw 00001dh adc0 - setting register rw 00001eh adc0 - extended con?uration register adecr rw 00001fh reserved - 000020h frt0 - data register of free-running timer tcdt0 rw 000021h frt0 - data register of free-running timer rw 000022h frt0 - control status register of free-running timer low tccsl0 tccs0 rw 000023h frt0 - control status register of free-running timer high tccsh0 rw 000024h frt1 - data register of free-running timer tcdt1 rw 000025h frt1 - data register of free-running timer rw 000026h frt1 - control status register of free-running timer low tccsl1 tccs1 rw 000027h frt1 - control status register of free-running timer high tccsh1 rw 000028h- 000033h reserved -
preliminary mb96350 series fme-mb96350 rev 5 24 2008-2-4 000034h ocu4 - output compare control status ocs4 rw 000035h ocu5 - output compare control status ocs5 rw 000036h ocu4 - compare register occp4 rw 000037h ocu4 - compare register rw 000038h ocu5 - compare register occp5 rw 000039h ocu5 - compare register rw 00003ah ocu6 - output compare control status ocs6 rw 00003bh ocu7 - output compare control status ocs7 rw 00003ch ocu6 - compare register occp6 rw 00003dh ocu6 - compare register rw 00003eh ocu7 - compare register occp7 rw 00003fh ocu7 - compare register rw 000040h icu0/icu1 - control status register ics01 rw 000041h icu0/icu1 - edge register ice01 rw 000042h icu0 - capture register low ipcpl0 ipcp0 r 000043h icu0 - capture register high ipcph0 r 000044h icu1 - capture register low ipcpl1 ipcp1 r 000045h icu1 - capture register high ipcph1 r 000046h - 00004bh reserved 00004ch icu4/icu5 - control status register ics45 rw 00004dh icu4/icu5 - edge register ice45 rw 00004eh icu4 - capture register low ipcpl4 ipcp4 r 00004fh icu4 - capture register high ipcph4 r 000050h icu5 - capture register low ipcpl5 ipcp5 r 000051h icu5 - capture register high ipcph5 r 000052h icu6/icu7 - control status register ics67 rw 000053h icu6/icu7 - edge register ice67 rw 000054h icu6 - capture register low ipcpl6 ipcp6 r 000055h icu6 - capture register high ipcph6 r i/o map mb96(f)35x (2 / 27) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 25 000056h icu7 - capture register low ipcpl7 ipcp7 r 000057h icu7 - capture register high ipcph7 r 000058h extint0 - external interrupt enable register enir0 rw 000059h extint0 - external interrupt interrupt request reg- ister eirr0 rw 00005ah extint0 - external interrupt level select low elvrl0 elvr0 rw 00005bh extint0 - external interrupt level select high elvrh0 rw 00005ch extint1 - external interrupt enable register enir1 rw 00005dh extint1 - external interrupt interrupt request reg- ister eirr1 rw 00005eh extint1 - external interrupt level select low elvrl1 elvr1 rw 00005fh extint1 - external interrupt level select high elvrh1 rw 000060h rlt0 - timer control status register low tmcsrl0 tmcsr0 rw 000061h rlt0 - timer control status register high tmcsrh0 rw 000062h rlt0 - reload register - for writing tmrlr0 w 000062h rlt0 - reload register - for reading tmr0 r 000063h rlt0 - reload register - for writing w 000063h rlt0 - reload register - for reading r 000064h rlt1 - timer control status register low tmcsrl1 tmcsr1 rw 000065h rlt1 - timer control status register high tmcsrh1 rw 000066h rlt1 - reload register - for writing tmrlr1 w 000066h rlt1 - reload register - for reading tmr1 r 000067h rlt1 - reload register - for writing w 000067h rlt1 - reload register - for reading r 000068h rlt2 - timer control status register low tmcsrl2 tmcsr2 rw 000069h rlt2 - timer control status register high tmcsrh2 rw 00006ah rlt2 - reload register - for writing tmrlr2 w 00006ah rlt2 - reload register - for reading tmr2 r 00006bh rlt2 - reload register - for writing w 00006bh rlt2 - reload register - for reading r 00006ch rlt3 - timer control status register low tmcsrl3 tmcsr3 rw i/o map mb96(f)35x (3 / 27) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96350 series fme-mb96350 rev 5 26 2008-2-4 00006dh rlt3 - timer control status register high tmcsrh3 rw 00006eh rlt3 - reload register - for writing tmrlr3 w 00006eh rlt3 - reload register - for reading tmr3 r 00006fh rlt3 - reload register - for writing w 00006fh rlt3 - reload register - for reading r 000070h rlt6 - timer control status register low (dedic. rlt for ppg) tmcsrl6 tmcsr6 rw 000071h rlt6 - timer control status register high (dedic. rlt for ppg) tmcsrh6 rw 000072h rlt6 - reload register (dedic. rlt for ppg) - for writing tmrlr6 w 000072h rlt6 - reload register (dedic. rlt for ppg) - for reading tmr6 r 000073h rlt6 - reload register (dedic. rlt for ppg) - for writing w 000073h rlt6 - reload register (dedic. rlt for ppg) - for reading r 000074h ppg3-ppg0 - general control register 1 low gcn1l0 gcn10 rw 000075h ppg3-ppg0 - general control register 1 high gcn1h0 rw 000076h ppg3-ppg0 - general control register 2 low gcn2l0 gcn20 rw 000077h ppg3-ppg0 - general control register 2 high gcn2h0 rw 000078h ppg0 - timer register ptmr0 r 000079h ppg0 - timer register r 00007ah ppg0 - period setting register pcsr0 w 00007bh ppg0 - period setting register w 00007ch ppg0 - duty cycle register pdut0 w 00007dh ppg0 - duty cycle register w 00007eh ppg0 - control status register low pcnl0 pcn0 rw 00007fh ppg0 - control status register high pcnh0 rw 000080h ppg1 - timer register ptmr1 r 000081h ppg1 - timer register r 000082h ppg1 - period setting register pcsr1 w i/o map mb96(f)35x (4 / 27) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 27 000083h ppg1 - period setting register w 000084h ppg1 - duty cycle register pdut1 w 000085h ppg1 - duty cycle register w 000086h ppg1 - control status register low pcnl1 pcn1 rw 000087h ppg1 - control status register high pcnh1 rw 000088h ppg2 - timer register ptmr2 r 000089h ppg2 - timer register r 00008ah ppg2 - period setting register pcsr2 w 00008bh ppg2 - period setting register w 00008ch ppg2 - duty cycle register pdut2 w 00008dh ppg2 - duty cycle register w 00008eh ppg2 - control status register low pcnl2 pcn2 rw 00008fh ppg2 - control status register high pcnh2 rw 000090h ppg3 - timer register ptmr3 r 000091h ppg3 - timer register r 000092h ppg3 - period setting register pcsr3 w 000093h ppg3 - period setting register w 000094h ppg3 - duty cycle register pdut3 w 000095h ppg3 - duty cycle register w 000096h ppg3 - control status register low pcnl3 pcn3 rw 000097h ppg3 - control status register high pcnh3 rw 000098h ppg7-ppg4 - general control register 1 low gcn1l1 gcn11 rw 000099h ppg7-ppg4 - general control register 1 high gcn1h1 rw 00009ah ppg7-ppg4 - general control register 2 low gcn2l1 gcn21 rw 00009bh ppg7-ppg4 - general control register 2 high gcn2h1 rw 00009ch ppg4 - timer register ptmr4 r 00009dh ppg4 - timer register r 00009eh ppg4 - period setting register pcsr4 w 00009fh ppg4 - period setting register w 0000a0h ppg4 - duty cycle register pdut4 w i/o map mb96(f)35x (5 / 27) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96350 series fme-mb96350 rev 5 28 2008-2-4 0000a1h ppg4 - duty cycle register w 0000a2h ppg4 - control status register low pcnl4 pcn4 rw 0000a3h ppg4 - control status register high pcnh4 rw 0000a4h ppg5 - timer register ptmr5 r 0000a5h ppg5 - timer register r 0000a6h ppg5 - period setting register pcsr5 w 0000a7h ppg5 - period setting register w 0000a8h ppg5 - duty cycle register pdut5 w 0000a9h ppg5 - duty cycle register w 0000aah ppg5 - control status register low pcnl5 pcn5 rw 0000abh ppg5 - control status register high pcnh5 rw 0000ach i2c0 - bus status register ibsr0 r 0000adh i2c0 - bus control register ibcr0 rw 0000aeh i2c0 - ten bit slave address register low itbal0 itba0 rw 0000afh i2c0 - ten bit slave address register high itbah0 rw 0000b0h i2c0 - ten bit address mask register low itmkl0 itmk0 rw 0000b1h i2c0 - ten bit address mask register high itmkh0 rw 0000b2h i2c0 - seven bit slave address register isba0 rw 0000b3h i2c0 - seven bit address mask register ismk0 rw 0000b4h i2c0 - data register idar0 rw 0000b5h i2c0 - clock control register iccr0 rw 0000b6h- 0000d3h reserved - 0000d4h usart2 - serial mode register smr2 rw 0000d5h usart2 - serial control register scr2 rw 0000d6h usart2 - tx register tdr2 w 0000d6h usart2 - rx register rdr2 r 0000d7h usart2 - serial status ssr2 rw 0000d8h usart2 - control/com. register eccr2 rw 0000d9h usart2 - ext. status register escr2 rw i/o map mb96(f)35x (6 / 27) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 29 0000dah usart2 - baud rate generator register low bgrl2 bgr2 rw 0000dbh usart2 - baud rate generator register high bgrh2 rw 0000dch usart2 - extended serial interrupt register esir2 rw 0000ddh reserved - 0000deh usart3 - serial mode register smr3 rw 0000dfh usart3 - serial control register scr3 rw 0000e0h usart3 - tx register tdr3 w 0000e0h usart3 - rx register rdr3 r 0000e1h usart3 - serial status ssr3 rw 0000e2h usart3 - control/com. register eccr3 rw 0000e3h usart3 - ext. status register escr3 rw 0000e4h usart3 - baud rate generator register low bgrl3 bgr3 rw 0000e5h usart3 - baud rate generator register high bgrh3 rw 0000e6h usart3 - extended serial interrupt register esir3 rw 0000e7h- 0000efh reserved - 0000f0h- 0000ffh external bus area extbus0 rw 000100h dma0 - buffer address pointer low byte bapl0 rw 000101h dma0 - buffer address pointer middle byte bapm0 rw 000102h dma0 - buffer address pointer high byte baph0 rw 000103h dma0 - dma control register dmacs0 rw 000104h dma0 - i/o register address pointer low byte ioal0 ioa0 rw 000105h dma0 - i/o register address pointer high byte ioah0 rw 000106h dma0 - data counter low byte dctl0 dct0 rw 000107h dma0 - data counter high byte dcth0 rw 000108h dma1 - buffer address pointer low byte bapl1 rw 000109h dma1 - buffer address pointer middle byte bapm1 rw 00010ah dma1 - buffer address pointer high byte baph1 rw 00010bh dma1 - dma control register dmacs1 rw 00010ch dma1 - i/o register address pointer low byte ioal1 ioa1 rw i/o map mb96(f)35x (7 / 27) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96350 series fme-mb96350 rev 5 30 2008-2-4 00010dh dma1 - i/o register address pointer high byte ioah1 rw 00010eh dma1 - data counter low byte dctl1 dct1 rw 00010fh dma1 - data counter high byte dcth1 rw 000110h dma2 - buffer address pointer low byte bapl2 rw 000111h dma2 - buffer address pointer middle byte bapm2 rw 000112h dma2 - buffer address pointer high byte baph2 rw 000113h dma2 - dma control register dmacs2 rw 000114h dma2 - i/o register address pointer low byte ioal2 ioa2 rw 000115h dma2 - i/o register address pointer high byte ioah2 rw 000116h dma2 - data counter low byte dctl2 dct2 rw 000117h dma2 - data counter high byte dcth2 rw 000118h dma3 - buffer address pointer low byte bapl3 rw 000119h dma3 - buffer address pointer middle byte bapm3 rw 00011ah dma3 - buffer address pointer high byte baph3 rw 00011bh dma3 - dma control register dmacs3 rw 00011ch dma3 - i/o register address pointer low byte ioal3 ioa3 rw 00011dh dma3 - i/o register address pointer high byte ioah3 rw 00011eh dma3 - data counter low byte dctl3 dct3 rw 00011fh dma3 - data counter high byte dcth3 rw 000120h- 00017fh reserved - 000180h- 00037fh cpu - general purpose registers (ram access) gpr_ram rw 000380h dma0 - interrupt select disel0 rw 000381h dma1 - interrupt select disel1 rw 000382h dma2 - interrupt select disel2 rw 000383h dma3 - interrupt select disel3 rw 000384h- 00038fh reserved - 000390h dma - status register low byte dsrl dsr rw 000391h dma - status register high byte dsrh rw i/o map mb96(f)35x (8 / 27) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 31 000392h dma - stop status register low byte dssrl dssr rw 000393h dma - stop status register high byte dssrh rw 000394h dma - enable register low byte derl der rw 000395h dma - enable register high byte derh rw 000396h- 00039fh reserved - 0003a0h interrupt level register ilr icr rw 0003a1h interrupt index register idx rw 0003a2h interrupt vector table base register low tbrl tbr rw 0003a3h interrupt vector table base register high tbrh rw 0003a4h delayed interrupt register dirr rw 0003a5h non maskable interrupt register nmi rw 0003a6h- 0003abh reserved - 0003ach edsu communication interrupt selection low edsu2l edsu2 rw 0003adh edsu communication interrupt selection high edsu2h rw 0003aeh rom mirror control register romm rw 0003afh edsu con?uration register edsu rw 0003b0h memory patch control/status register ch 0/1 pfcs0 rw 0003b1h memory patch control/status register ch 0/1 rw 0003b2h memory patch control/status register ch 2/3 pfcs1 rw 0003b3h memory patch control/status register ch 2/3 rw 0003b4h memory patch control/status register ch 4/5 pfcs2 rw 0003b5h memory patch control/status register ch 4/5 rw 0003b6h memory patch control/status register ch 6/7 pfcs3 rw 0003b7h memory patch control/status register ch 6/7 rw 0003b8h memory patch function - patch address 0 low pfal0 rw 0003b9h memory patch function - patch address 0 middle pfam0 rw 0003bah memory patch function - patch address 0 high pfah0 rw 0003bbh memory patch function - patch address 1 low pfal1 rw 0003bch memory patch function - patch address 1 middle pfam1 rw i/o map mb96(f)35x (9 / 27) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96350 series fme-mb96350 rev 5 32 2008-2-4 0003bdh memory patch function - patch address 1 high pfah1 rw 0003beh memory patch function - patch address 2 low pfal2 rw 0003bfh memory patch function - patch address 2 middle pfam2 rw 0003c0h memory patch function - patch address 2 high pfah2 rw 0003c1h memory patch function - patch address 3 low pfal3 rw 0003c2h memory patch function - patch address 3 middle pfam3 rw 0003c3h memory patch function - patch address 3 high pfah3 rw 0003c4h memory patch function - patch address 4 low pfal4 rw 0003c5h memory patch function - patch address 4 middle pfam4 rw 0003c6h memory patch function - patch address 4 high pfah4 rw 0003c7h memory patch function - patch address 5 low pfal5 rw 0003c8h memory patch function - patch address 5 middle pfam5 rw 0003c9h memory patch function - patch address 5 high pfah5 rw 0003cah memory patch function - patch address 6 low pfal6 rw 0003cbh memory patch function - patch address 6 middle pfam6 rw 0003cch memory patch function - patch address 6 high pfah6 rw 0003cdh memory patch function - patch address 7 low pfal7 rw 0003ceh memory patch function - patch address 7 middle pfam7 rw 0003cfh memory patch function - patch address 7 high pfah7 rw 0003d0h memory patch function - patch data 0 low pfdl0 pfd0 rw 0003d1h memory patch function - patch data 0 high pfdh0 rw 0003d2h memory patch function - patch data 1 low pfdl1 pfd1 rw 0003d3h memory patch function - patch data 1 high pfdh1 rw 0003d4h memory patch function - patch data 2 low pfdl2 pfd2 rw 0003d5h memory patch function - patch data 2 high pfdh2 rw 0003d6h memory patch function - patch data 3 low pfdl3 pfd3 rw 0003d7h memory patch function - patch data 3 high pfdh3 rw 0003d8h memory patch function - patch data 4 low pfdl4 pfd4 rw 0003d9h memory patch function - patch data 4 high pfdh4 rw 0003dah memory patch function - patch data 5 low pfdl5 pfd5 rw i/o map mb96(f)35x (10 / 27) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 33 0003dbh memory patch function - patch data 5 high pfdh5 rw 0003dch memory patch function - patch data 6 low pfdl6 pfd6 rw 0003ddh memory patch function - patch data 6 high pfdh6 rw 0003deh memory patch function - patch data 7 low pfdl7 pfd7 rw 0003dfh memory patch function - patch data 7 high pfdh7 rw 0003e0h- 0003f0h reserved - 0003f1h memory control status register a mcsra rw 0003f2h memory timing con?uration register a low mtcral mtcra rw 0003f3h memory timing con?uration register a high mtcrah rw 0003f4h- 0003f8h reserved - 0003f9h flash memory write control register 1 fmwc1 rw 0003fah flash memory write control register 2 fmwc2 rw 0003fbh flash memory write control register 3 fmwc3 rw 0003fch flash memory write control register 4 fmwc4 rw 0003fdh flash memory write control register 5 fmwc5 rw 0003feh- 0003ffh reserved - 000400h standby mode control register smcr rw 000401h clock select register cksr rw 000402h clock stabilisation select register ckssr rw 000403h clock monitor register ckmr r 000404h clock frequency control register low ckfcrl ckfcr rw 000405h clock frequency control register high ckfcrh rw 000406h pll control register low pllcrl pllcr rw 000407h pll control register high pllcrh rw 000408h rc clock timer control register rctcr rw 000409h main clock timer control register mctcr rw 00040ah sub clock timer control register sctcr rw i/o map mb96(f)35x (11 / 27) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96350 series fme-mb96350 rev 5 34 2008-2-4 00040bh reset cause and clock status register with clear function rccsrc r 00040ch reset con?uration register rcr rw 00040dh reset cause and clock status register rccsr r 00040eh watch dog timer con?uration register wdtc rw 00040fh watch dog timer clear pattern register wdtcp w 000410h- 000414h reserved - 000415h clock output activation register coar rw 000416h clock output con?uration register 0 cocr0 rw 000417h clock output con?uration register 1 cocr1 rw 000418h clock modulator control register cmcr rw 000419h reserved - 00041ah clock modulator parameter register low cmprl cmpr rw 00041bh clock modulator parameter register high cmprh rw 00041ch- 00042bh reserved - 00042ch voltage regulator control register vrcr rw 00042dh clock input and lvd control register cilcr rw 00042eh- 00042fh reserved - 000430h i/o port p00 - data direction register ddr00 rw 000431h i/o port p01 - data direction register ddr01 rw 000432h i/o port p02 - data direction register ddr02 rw 000433h i/o port p03 - data direction register ddr03 rw 000434h i/o port p04 - data direction register ddr04 rw 000435h i/o port p05 - data direction register ddr05 rw 000436h i/o port p06 - data direction register ddr06 rw 000437h- 000443h reserved - 000444h i/o port p00 - port input enable register pier00 rw 000445h i/o port p01 - port input enable register pier01 rw i/o map mb96(f)35x (12 / 27) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 35 000446h i/o port p02 - port input enable register pier02 rw 000447h i/o port p03 - port input enable register pier03 rw 000448h i/o port p04 - port input enable register pier04 rw 000449h i/o port p05 - port input enable register pier05 rw 00044ah i/o port p06 - port input enable register pier06 rw 00044bh- 000457h reserved - 000458h i/o port p00 - port input level register pilr00 rw 000459h i/o port p01 - port input level register pilr01 rw 00045ah i/o port p02 - port input level register pilr02 rw 00045bh i/o port p03 - port input level register pilr03 rw 00045ch i/o port p04 - port input level register pilr04 rw 00045dh i/o port p05 - port input level register pilr05 rw 00045eh i/o port p06 - port input level register pilr06 rw 00045fh- 00046bh reserved - 00046ch i/o port p00 - extended port input level register epilr00 rw 00046dh i/o port p01 - extended port input level register epilr01 rw 00046eh i/o port p02 - extended port input level register epilr02 rw 00046fh i/o port p03 - extended port input level register epilr03 rw 000470h i/o port p04 - extended port input level register epilr04 rw 000471h i/o port p05 - extended port input level register epilr05 rw 000472h i/o port p06 - extended port input level register epilr06 rw 000473h- 00047fh reserved - 000480h i/o port p00 - port output drive register podr00 rw 000481h i/o port p01 - port output drive register podr01 rw 000482h i/o port p02 - port output drive register podr02 rw 000483h i/o port p03 - port output drive register podr03 rw 000484h i/o port p04 - port output drive register podr04 rw 000485h i/o port p05 - port output drive register podr05 rw i/o map mb96(f)35x (13 / 27) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96350 series fme-mb96350 rev 5 36 2008-2-4 000486h i/o port p06 - port output drive register podr06 rw 000487h- 0004a7h reserved - 0004a8h i/o port p00 - pull-up resistor control register pucr00 rw 0004a9h i/o port p01 - pull-up resistor control register pucr01 rw 0004aah i/o port p02 - pull-up resistor control register pucr02 rw 0004abh i/o port p03 - pull-up resistor control register pucr03 rw 0004ach i/o port p04 - pull-up resistor control register pucr04 rw 0004adh i/o port p05 - pull-up resistor control register pucr05 rw 0004aeh i/o port p06 - pull-up resistor control register pucr06 rw 0004afh- 0004bbh reserved - 0004bch i/o port p00 - external pin state register epsr00 r 0004bdh i/o port p01 - external pin state register epsr01 r 0004beh i/o port p02 - external pin state register epsr02 r 0004bfh i/o port p03 - external pin state register epsr03 r 0004c0h i/o port p04 - external pin state register epsr04 r 0004c1h i/o port p05 - external pin state register epsr05 r 0004c2h i/o port p06 - external pin state register epsr06 r 0004c3h- 0004cfh reserved - 0004d0h adc analog input enable register 0 ader0 rw 0004d1h adc analog input enable register 1 ader1 rw 0004d2h adc analog input enable register 2 ader2 rw 0004d3h adc analog input enable register 3 ader3 rw 0004d4h adc analog input enable register 4 ader4 rw 0004d5h reserved - 0004d6h peripheral resource relocation register 0 prrr0 rw 0004d7h peripheral resource relocation register 1 prrr1 rw 0004d8h peripheral resource relocation register 2 prrr2 rw 0004d9h peripheral resource relocation register 3 prrr3 rw i/o map mb96(f)35x (14 / 27) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 37 0004dah peripheral resource relocation register 4 prrr4 rw 0004dbh peripheral resource relocation register 5 prrr5 rw 0004dch peripheral resource relocation register 6 prrr6 rw 0004ddh peripheral resource relocation register 7 prrr7 rw 0004deh peripheral resource relocation register 8 prrr8 rw 0004dfh peripheral resource relocation register 9 prrr9 rw 0004e0h rtc - sub second register l wtbrl0 wtbr0 rw 0004e1h rtc - sub second register m wtbrh0 rw 0004e2h rtc - sub-second register h wtbr1 rw 0004e3h rtc - second register wtsr rw 0004e4h rtc - minutes wtmr rw 0004e5h rtc - hour wthr rw 0004e6h rtc - timer control extended register wtcer rw 0004e7h rtc - clock select register wtcksr rw 0004e8h rtc - timer control register low wtcrl wtcr rw 0004e9h rtc - timer control register high wtcrh rw 0004eah cal - calibration unit control register cucr rw 0004ebh reserved - 0004ech cal - duration timer data register low cutdl cutd rw 0004edh cal - duration timer data register high cutdh rw 0004eeh cal - calibration timer register 2 low cutr2l cutr2 r 0004efh cal - calibration timer register 2 high cutr2h r 0004f0h cal - calibration timer register 1 low cutr1l cutr1 r 0004f1h cal - calibration timer register 1 high cutr1h r 0004f2h- 0004f9h reserved - 0004fah rlt - timer input select (for cascading) tmisr rw 0004fbh- 00053dh reserved - 00053eh usart7 - serial mode register smr7 rw 00053fh usart7 - serial control register scr7 rw i/o map mb96(f)35x (15 / 27) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96350 series fme-mb96350 rev 5 38 2008-2-4 000540h usart7 - serial tx register tdr7 w 000540h usart7 - serial rx register rdr7 r 000541h usart7 - serial status register ssr7 rw 000542h usart7 - ext. control/com. register eccr7 rw 000543h usart7 - ext. status com. register escr7 rw 000544h usart7 - baud rate generator register low bgrl7 bgr7 rw 000545h usart7 - baud rate generator register high bgrh7 rw 000546h usart7 - extended serial interrupt register esir7 rw 000547h reserved - 000548h usart8 - serial mode register smr8 rw 000549h usart8 - serial control register scr8 rw 00054ah usart8 - serial tx register tdr8 w 00054ah usart8 - serial rx register rdr8 r 00054bh usart8 - serial status register ssr8 rw 00054ch usart8 - ext. control/com. register eccr8 rw 00054dh usart8 - ext. status com. register escr8 rw 00054eh usart8 - baud rate generator register low bgrl8 bgr8 rw 00054fh usart8 - baud rate generator register high bgrh8 rw 000550h usart8 - extended serial interrupt register esir8 rw 000551h- 000563h reserved - 000564h ppg6 - timer register ptmr6 r 000565h ppg6 - timer register r 000566h ppg6 - period setting register pcsr6 w 000567h ppg6 - period setting register w 000568h ppg6 - duty cycle register pdut6 w 000569h ppg6 - duty cycle register w 00056ah ppg6 - control status register low pcnl6 pcn6 rw 00056bh ppg6 - control status register high pcnh6 rw 00056ch ppg7 - timer register ptmr7 r i/o map mb96(f)35x (16 / 27) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 39 00056dh ppg7 - timer register r 00056eh ppg7 - period setting register pcsr7 w 00056fh ppg7 - period setting register w 000570h ppg7 - duty cycle register pdut7 w 000571h ppg7 - duty cycle register w 000572h ppg7 - control status register low pcnl7 pcn7 rw 000573h ppg7 - control status register high pcnh7 rw 000574h ppg11-ppg8 - general control register 1 low gcn1l2 gcn12 rw 000575h ppg11-ppg8 - general control register 1 high gcn1h2 rw 000576h ppg11-ppg8 - general control register 2 low gcn2l2 gcn22 rw 000577h ppg11-ppg8 - general control register 2 high gcn2h2 rw 000578h ppg8 - timer register ptmr8 r 000579h ppg8 - timer register r 00057ah ppg8 - period setting register pcsr8 w 00057bh ppg8 - period setting register w 00057ch ppg8 - duty cycle register pdut8 w 00057dh ppg8 - duty cycle register w 00057eh ppg8 - control status register low pcnl8 pcn8 rw 00057fh ppg8 - control status register high pcnh8 rw 000580h ppg9 - timer register ptmr9 r 000581h ppg9 - timer register r 000582h ppg9 - period setting register pcsr9 w 000583h ppg9 - period setting register w 000584h ppg9 - duty cycle register pdut9 w 000585h ppg9 - duty cycle register w 000586h ppg9 - control status register low pcnl9 pcn9 rw 000587h ppg9 - control status register high pcnh9 rw 000588h ppg10 - timer register ptmr10 r 000589h ppg10 - timer register r 00058ah ppg10 - period setting register pcsr10 w i/o map mb96(f)35x (17 / 27) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96350 series fme-mb96350 rev 5 40 2008-2-4 00058bh ppg10 - period setting register w 00058ch ppg10 - duty cycle register pdut10 w 00058dh ppg10 - duty cycle register w 00058eh ppg10 - control status register low pcnl10 pcn10 rw 00058fh ppg10 - control status register high pcnh10 rw 000590h ppg11 - timer register ptmr11 r 000591h ppg11 - timer register r 000592h ppg11 - period setting register pcsr11 w 000593h ppg11 - period setting register w 000594h ppg11 - duty cycle register pdut11 w 000595h ppg11 - duty cycle register w 000596h ppg11 - control status register low pcnl11 pcn11 rw 000597h ppg11 - control status register high pcnh11 rw 000598h ppg15-ppg12 - general control register 1 low gcn1l3 gcn13 rw 000599h ppg15-ppg12 - general control register 1 high gcn1h3 rw 00059ah ppg15-ppg12 - general control register 2 low gcn2l3 gcn23 rw 00059bh ppg15-ppg12 - general control register 2 high gcn2h3 rw 00059ch ppg12 - timer register ptmr12 r 00059dh ppg12 - timer register r 00059eh ppg12 - period setting register pcsr12 w 00059fh ppg12 - period setting register w 0005a0h ppg12 - duty cycle register pdut12 w 0005a1h ppg12 - duty cycle register w 0005a2h ppg12 - control status register low pcnl12 pcn12 rw 0005a3h ppg12 - control status register high pcnh12 rw 0005a4h ppg13 - timer register ptmr13 r 0005a5h ppg13 - timer register r 0005a6h ppg13 - period setting register pcsr13 w 0005a7h ppg13 - period setting register w 0005a8h ppg13 - duty cycle register pdut13 w i/o map mb96(f)35x (18 / 27) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 41 0005a9h ppg13 - duty cycle register w 0005aah ppg13 - control status register low pcnl13 pcn13 rw 0005abh ppg13 - control status register high pcnh13 rw 0005ach ppg14 - timer register ptmr14 r 0005adh ppg14 - timer register r 0005aeh ppg14 - period setting register pcsr14 w 0005afh ppg14 - period setting register w 0005b0h ppg14 - duty cycle register pdut14 w 0005b1h ppg14 - duty cycle register w 0005b2h ppg14 - control status register low pcnl14 pcn14 rw 0005b3h ppg14 - control status register high pcnh14 rw 0005b4h ppg15 - timer register ptmr15 r 0005b5h ppg15 - timer register r 0005b6h ppg15 - period setting register pcsr15 w 0005b7h ppg15 - period setting register w 0005b8h ppg15 - duty cycle register pdut15 w 0005b9h ppg15 - duty cycle register w 0005bah ppg15 - control status register low pcnl15 pcn15 rw 0005bbh ppg15 - control status register high pcnh15 rw 0005bch ppg19-ppg16 - general control register 1 low gcn1l4 gcn14 rw 0005bdh ppg19-ppg16 - general control register 1 high gcn1h4 rw 0005beh ppg19-ppg16 - general control register 2 low gcn2l4 gcn24 rw 0005bfh ppg19-ppg16 - general control register 2 high gcn2h4 rw 0005c0h ppg16 - timer register ptmr16 r 0005c1h ppg16 - timer register r 0005c2h ppg16 - period setting register pcsr16 w 0005c3h ppg16 - period setting register w 0005c4h ppg16 - duty cycle register pdut16 w 0005c5h ppg16 - duty cycle register w 0005c6h ppg16 - control status register low pcnl16 pcn16 rw i/o map mb96(f)35x (19 / 27) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96350 series fme-mb96350 rev 5 42 2008-2-4 0005c7h ppg16 - control status register high pcnh16 rw 0005c8h ppg17 - timer register ptmr17 r 0005c9h ppg17 - timer register r 0005cah ppg17 - period setting register pcsr17 w 0005cbh ppg17 - period setting register w 0005cch ppg17 - duty cycle register pdut17 w 0005cdh ppg17 - duty cycle register w 0005ceh ppg17 - control status register low pcnl17 pcn17 rw 0005cfh ppg17 - control status register high pcnh17 rw 0005d0h ppg18 - timer register ptmr18 r 0005d1h ppg18 - timer register r 0005d2h ppg18 - period setting register pcsr18 w 0005d3h ppg18 - period setting register w 0005d4h ppg18 - duty cycle register pdut18 w 0005d5h ppg18 - duty cycle register w 0005d6h ppg18 - control status register low pcnl18 pcn18 rw 0005d7h ppg18 - control status register high pcnh18 rw 0005d8h ppg19 - timer register ptmr19 r 0005d9h ppg19 - timer register r 0005dah ppg19 - period setting register pcsr19 w 0005dbh ppg19 - period setting register w 0005dch ppg19 - duty cycle register pdut19 w 0005ddh ppg19 - duty cycle register w 0005deh ppg19 - control status register low pcnl19 pcn19 rw 0005dfh ppg19 - control status register high pcnh19 rw 0005e0h- 00065fh reserved - 000660h peripheral resource relocation register 10 prrr10 rw 000661h peripheral resource relocation register 11 prrr11 rw 000662h peripheral resource relocation register 12 prrr12 rw i/o map mb96(f)35x (20 / 27) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 43 000663h peripheral resource relocation register 13 prrr13 w 000664h- 0006dfh reserved - 0006e0h external bus - area con?uration register 0 low eacl0 eac0 rw 0006e1h external bus - area con?uration register 0 high each0 rw 0006e2h external bus - area con?uration register 1 low eacl1 eac1 rw 0006e3h external bus - area con?uration register 1 high each1 rw 0006e4h external bus - area con?uration register 2 low eacl2 eac2 rw 0006e5h external bus - area con?uration register 2 high each2 rw 0006e6h external bus - area con?uration register 3 low eacl3 eac3 rw 0006e7h external bus - area con?uration register 3 high each3 rw 0006e8h external bus - area con?uration register 4 low eacl4 eac4 rw 0006e9h external bus - area con?uration register 4 high each4 rw 0006eah external bus - area con?uration register 5 low eacl5 eac5 rw 0006ebh external bus - area con?uration register 5 high each5 rw 0006ech external bus - area select register 2 eas2 rw 0006edh external bus - area select register 3 eas3 rw 0006eeh external bus - area select register 4 eas4 rw 0006efh external bus - area select register 5 eas5 rw 0006f0h external bus - mode register ebm rw 0006f1h external bus - clock and function register ebcf rw 0006f2h external bus - address output enable register 0 ebae0 rw 0006f3h external bus - address output enable register 1 ebae1 rw 0006f4h external bus - address output enable register 2 ebae2 rw 0006f5h external bus - control signal register ebcs rw 0006f6h- 0007ffh reserved - 000800h can1 - control register low ctrlrl1 ctrlr1 rw 000801h can1 - control register high (reserved) ctrlrh1 r 000802h can1 - status register low statrl1 statr1 rw 000803h can1 - status register high (reserved) statrh1 r i/o map mb96(f)35x (21 / 27) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96350 series fme-mb96350 rev 5 44 2008-2-4 000804h can1 - error counter low (transmit) errcntl1 errcnt1 r 000805h can1 - error counter high (receive) errcnth1 r 000806h can1 - bit timing register low btrl1 btr1 rw 000807h can1 - bit timing register high btrh1 rw 000808h can1 - interrupt register low intrl1 intr1 r 000809h can1 - interrupt register high intrh1 r 00080ah can1 - test register low testrl1 testr1 rw 00080bh can1 - test register high (reserved) testrh1 r 00080ch can1 - brp extension register low brperl1 brper1 rw 00080dh can1 - brp extension register high (reserved) brperh1 r 00080eh- 00080fh reserved - 000810h can1 - if1 command request register low if1creql1 if1creq1 rw 000811h can1 - if1 command request register high if1creqh1 rw 000812h can1 - if1 command mask register low if1cmskl1 if1cmsk1 rw 000813h can1 - if1 command mask register high (re- served) if1cmskh1 r 000814h can1 - if1 mask 1 register low if1msk1l1 if1msk11 rw 000815h can1 - if1 mask 1 register high if1msk1h1 rw 000816h can1 - if1 mask 2 register low if1msk2l1 if1msk21 rw 000817h can1 - if1 mask 2 register high if1msk2h1 rw 000818h can1 - if1 arbitration 1 register low if1arb1l1 if1arb11 rw 000819h can1 - if1 arbitration 1 register high if1arb1h1 rw 00081ah can1 - if1 arbitration 2 register low if1arb2l1 if1arb21 rw 00081bh can1 - if1 arbitration 2 register high if1arb2h1 rw 00081ch can1 - if1 message control register low if1mctrl1 if1mctr1 rw 00081dh can1 - if1 message control register high if1mctrh1 rw 00081eh can1 - if1 data a1 low if1dta1l1 if1dta11 rw 00081fh can1 - if1 data a1 high if1dta1h1 rw 000820h can1 - if1 data a2 low if1dta2l1 if1dta21 rw 000821h can1 - if1 data a2 high if1dta2h1 rw i/o map mb96(f)35x (22 / 27) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 45 000822h can1 - if1 data b1 low if1dtb1l1 if1dtb11 rw 000823h can1 - if1 data b1 high if1dtb1h1 rw 000824h can1 - if1 data b2 low if1dtb2l1 if1dtb21 rw 000825h can1 - if1 data b2 high if1dtb2h1 rw 000826h- 00083fh reserved - 000840h can1 - if2 command request register low if2creql1 if2creq1 rw 000841h can1 - if2 command request register high if2creqh1 rw 000842h can1 - if2 command mask register low if2cmskl1 if2cmsk1 rw 000843h can1 - if2 command mask register high (re- served) if2cmskh1 r 000844h can1 - if2 mask 1 register low if2msk1l1 if2msk11 rw 000845h can1 - if2 mask 1 register high if2msk1h1 rw 000846h can1 - if2 mask 2 register low if2msk2l1 if2msk21 rw 000847h can1 - if2 mask 2 register high if2msk2h1 rw 000848h can1 - if2 arbitration 1 register low if2arb1l1 if2arb11 rw 000849h can1 - if2 arbitration 1 register high if2arb1h1 rw 00084ah can1 - if2 arbitration 2 register low if2arb2l1 if2arb21 rw 00084bh can1 - if2 arbitration 2 register high if2arb2h1 rw 00084ch can1 - if2 message control register low if2mctrl1 if2mctr1 rw 00084dh can1 - if2 message control register high if2mctrh1 rw 00084eh can1 - if2 data a1 low if2dta1l1 if2dta11 rw 00084fh can1 - if2 data a1 high if2dta1h1 rw 000850h can1 - if2 data a2 low if2dta2l1 if2dta21 rw 000851h can1 - if2 data a2 high if2dta2h1 rw 000852h can1 - if2 data b1 low if2dtb1l1 if2dtb11 rw 000853h can1 - if2 data b1 high if2dtb1h1 rw 000854h can1 - if2 data b2 low if2dtb2l1 if2dtb21 rw 000855h can1 - if2 data b2 high if2dtb2h1 rw 000856h- 00087fh reserved - i/o map mb96(f)35x (23 / 27) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96350 series fme-mb96350 rev 5 46 2008-2-4 000880h can1 - transmission request 1 register low treqr1l1 treqr11 r 000881h can1 - transmission request 1 register high treqr1h1 r 000882h can1 - transmission request 2 register low treqr2l1 treqr21 r 000883h can1 - transmission request 2 register high treqr2h1 r 000884h- 00088fh reserved - 000890h can1 - new data 1 register low newdt1l1 newdt11 r 000891h can1 - new data 1 register high newdt1h1 r 000892h can1 - new data 2 register low newdt2l1 newdt21 r 000893h can1 - new data 2 register high newdt2h1 r 000894h- 00089fh reserved - 0008a0h can1 - interrupt pending 1 register low intpnd1l1 intpnd11 r 0008a1h can1 - interrupt pending 1 register high intpnd1h1 r 0008a2h can1 - interrupt pending 2 register low intpnd2l1 intpnd21 r 0008a3h can1 - interrupt pending 2 register high intpnd2h1 r 0008a4h- 0008afh reserved - 0008b0h can1 - message valid 1 register low msgval1l1 msgval11 r 0008b1h can1 - message valid 1 register high msgval1h1 r 0008b2h can1 - message valid 2 register low msgval2l1 msgval21 r 0008b3h can1 - message valid 2 register high msgval2h1 r 0008b4h- 0008cdh reserved - 0008ceh can1 - output enable register coer1 rw 0008cfh- 0008ffh reserved - 000900h can2 - control register low ctrlrl2 ctrlr2 rw 000901h can2 - control register high (reserved) ctrlrh2 r 000902h can2 - status register low statrl2 statr2 rw 000903h can2 - status register high (reserved) statrh2 r 000904h can2 - error counter low (transmit) errcntl2 errcnt2 r i/o map mb96(f)35x (24 / 27) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 47 000905h can2 - error counter high (receive) errcnth2 r 000906h can2 - bit timing register low btrl2 btr2 rw 000907h can2 - bit timing register high btrh2 rw 000908h can2 - interrupt register low intrl2 intr2 r 000909h can2 - interrupt register high intrh2 r 00090ah can2 - test register low testrl2 testr2 rw 00090bh can2 - test register high (reserved) testrh2 r 00090ch can2 - brp extension register low brperl2 brper2 rw 00090dh can2 - brp extension register high (reserved) brperh2 r 00090eh- 00090fh reserved - 000910h can2 - if1 command request register low if1creql2 if1creq2 rw 000911h can2 - if1 command request register high if1creqh2 rw 000912h can2 - if1 command mask register low if1cmskl2 if1cmsk2 rw 000913h can2 - if1 command mask register high (re- served) if1cmskh2 r 000914h can2 - if1 mask 1 register low if1msk1l2 if1msk12 rw 000915h can2 - if1 mask 1 register high if1msk1h2 rw 000916h can2 - if1 mask 2 register low if1msk2l2 if1msk22 rw 000917h can2 - if1 mask 2 register high if1msk2h2 rw 000918h can2 - if1 arbitration 1 register low if1arb1l2 if1arb12 rw 000919h can2 - if1 arbitration 1 register high if1arb1h2 rw 00091ah can2 - if1 arbitration 2 register low if1arb2l2 if1arb22 rw 00091bh can2 - if1 arbitration 2 register high if1arb2h2 rw 00091ch can2 - if1 message control register low if1mctrl2 if1mctr2 rw 00091dh can2 - if1 message control register high if1mctrh2 rw 00091eh can2 - if1 data a1 low if1dta1l2 if1dta12 rw 00091fh can2 - if1 data a1 high if1dta1h2 rw 000920h can2 - if1 data a2 low if1dta2l2 if1dta22 rw 000921h can2 - if1 data a2 high if1dta2h2 rw 000922h can2 - if1 data b1 low if1dtb1l2 if1dtb12 rw i/o map mb96(f)35x (25 / 27) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96350 series fme-mb96350 rev 5 48 2008-2-4 000923h can2 - if1 data b1 high if1dtb1h2 rw 000924h can2 - if1 data b2 low if1dtb2l2 if1dtb22 rw 000925h can2 - if1 data b2 high if1dtb2h2 rw 000926h- 00093fh reserved - 000940h can2 - if2 command request register low if2creql2 if2creq2 rw 000941h can2 - if2 command request register high if2creqh2 rw 000942h can2 - if2 command mask register low if2cmskl2 if2cmsk2 rw 000943h can2 - if2 command mask register high (re- served) if2cmskh2 r 000944h can2 - if2 mask 1 register low if2msk1l2 if2msk12 rw 000945h can2 - if2 mask 1 register high if2msk1h2 rw 000946h can2 - if2 mask 2 register low if2msk2l2 if2msk22 rw 000947h can2 - if2 mask 2 register high if2msk2h2 rw 000948h can2 - if2 arbitration 1 register low if2arb1l2 if2arb12 rw 000949h can2 - if2 arbitration 1 register high if2arb1h2 rw 00094ah can2 - if2 arbitration 2 register low if2arb2l2 if2arb22 rw 00094bh can2 - if2 arbitration 2 register high if2arb2h2 rw 00094ch can2 - if2 message control register low if2mctrl2 if2mctr2 rw 00094dh can2 - if2 message control register high if2mctrh2 rw 00094eh can2 - if2 data a1 low if2dta1l2 if2dta12 rw 00094fh can2 - if2 data a1 high if2dta1h2 rw 000950h can2 - if2 data a2 low if2dta2l2 if2dta22 rw 000951h can2 - if2 data a2 high if2dta2h2 rw 000952h can2 - if2 data b1 low if2dtb1l2 if2dtb12 rw 000953h can2 - if2 data b1 high if2dtb1h2 rw 000954h can2 - if2 data b2 low if2dtb2l2 if2dtb22 rw 000955h can2 - if2 data b2 high if2dtb2h2 rw 000956h- 00097fh reserved - 000980h can2 - transmission request 1 register low treqr1l2 treqr12 r i/o map mb96(f)35x (26 / 27) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 49 000981h can2 - transmission request 1 register high treqr1h2 r 000982h can2 - transmission request 2 register low treqr2l2 treqr22 r 000983h can2 - transmission request 2 register high treqr2h2 r 000984h- 00098fh reserved - 000990h can2 - new data 1 register low newdt1l2 newdt12 r 000991h can2 - new data 1 register high newdt1h2 r 000992h can2 - new data 2 register low newdt2l2 newdt22 r 000993h can2 - new data 2 register high newdt2h2 r 000994h- 00099fh reserved - 0009a0h can2 - interrupt pending 1 register low intpnd1l2 intpnd12 r 0009a1h can2 - interrupt pending 1 register high intpnd1h2 r 0009a2h can2 - interrupt pending 2 register low intpnd2l2 intpnd22 r 0009a3h can2 - interrupt pending 2 register high intpnd2h2 r 0009a4h- 0009afh reserved - 0009b0h can2 - message valid 1 register low msgval1l2 msgval12 r 0009b1h can2 - message valid 1 register high msgval1h2 r 0009b2h can2 - message valid 2 register low msgval2l2 msgval22 r 0009b3h can2 - message valid 2 register high msgval2h2 r 0009b4h- 0009cdh reserved - 0009ceh can2 - output enable register coer2 rw 0009cfh- 000bffh reserved - i/o map mb96(f)35x (27 / 27) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96350 series fme-mb96350 rev 5 50 2008-2-4 interrupt vector table interrupt vector table mb96(f)35x (1 / 3) vector number offset in vector ta- ble vector name cleared by dma index in icr to pro- gram description 0 3fc callv0 no - 1 3f8 callv1 no - 2 3f4 callv2 no - 3 3f0 callv3 no - 4 3ec callv4 no - 5 3e8 callv5 no - 6 3e4 callv6 no - 7 3e0 callv7 no - 8 3dc reset no - 9 3d8 int9 no - 10 3d4 exception no - 11 3d0 nmi no - non-maskable interrupt 12 3cc dly no 12 delayed interrupt 13 3c8 rc_timer no 13 rc timer 14 3c4 mc_timer no 14 main clock timer 15 3c0 sc_timer no 15 sub clock timer 16 3bc pll_unlock no 16 reserved 17 3b8 extint0 yes 17 external interrupt 0 18 3b4 reserved 19 3b0 extint2 yes 19 external interrupt 2 20 3ac extint3 yes 20 external interrupt 3 21 3a8 extint4 yes 21 external interrupt 4 22 3a4 reserved 23 3a0 extint7 yes 23 external interrupt 7 24 39c extint8 yes 24 external interrupt 8 25 398 extint9 yes 25 external interrupt 9 26 394 extint10 yes 26 external interrupt 10 27 390 extint11 yes 27 external interrupt 11 28 38c extint12 yes 28 external interrupt 12 29 388 extint13 yes 29 external interrupt 13 30 384 extint14 yes 30 external interrupt 14 31 380 extint15 yes 31 external interrupt 15 32 37c can1 no 32 can controller 1
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 51 33 378 can2 no 33 can controller 2 34 374 ppg0 yes 34 programmable pulse generator 0 35 370 ppg1 yes 35 programmable pulse generator 1 36 36c ppg2 yes 36 programmable pulse generator 2 37 368 ppg3 yes 37 programmable pulse generator 3 38 364 ppg4 yes 38 programmable pulse generator 4 39 360 ppg5 yes 39 programmable pulse generator 5 40 35c ppg6 yes 40 programmable pulse generator 6 41 358 ppg7 yes 41 programmable pulse generator 7 42 354 ppg8 yes 42 programmable pulse generator 8 43 350 ppg9 yes 43 programmable pulse generator 9 44 34c ppg10 yes 44 programmable pulse generator 10 45 348 ppg11 yes 45 programmable pulse generator 11 46 344 ppg12 yes 46 programmable pulse generator 12 47 340 ppg13 yes 47 programmable pulse generator 13 48 33c ppg14 yes 48 programmable pulse generator 14 49 338 ppg15 yes 49 programmable pulse generator 15 50 334 ppg16 yes 50 programmable pulse generator 16 51 330 ppg17 yes 51 programmable pulse generator 17 52 32c ppg18 yes 52 programmable pulse generator 18 53 328 ppg19 yes 53 programmable pulse generator 19 54 324 rlt0 yes 54 reload timer 0 55 320 rlt1 yes 55 reload timer 1 56 31c rlt2 yes 56 reload timer 2 57 318 rlt3 yes 57 reload timer 3 58 314 ppgrlt yes 58 reload timer 6 - dedicated for ppg 59 310 icu0 yes 59 input capture unit 0 60 30c icu1 yes 60 input capture unit 1 61 308 reserved 62 304 reserved 63 300 icu4 yes 63 input capture unit 4 64 2fc icu5 yes 64 input capture unit 5 65 2f8 icu6 yes 65 input capture unit 6 66 2f4 icu7 yes 66 input capture unit 7 67 2f0 reserved interrupt vector table mb96(f)35x (2 / 3) vector number offset in vector ta- ble vector name cleared by dma index in icr to pro- gram description
preliminary mb96350 series fme-mb96350 rev 5 52 2008-2-4 68 2ec reserved 69 2e8 reserved 70 2e4 reserved 71 2e0 ocu4 yes 71 output compare unit 4 72 2dc ocu5 yes 72 output compare unit 5 73 2d8 ocu6 yes 73 output compare unit 6 74 2d4 ocu7 yes 74 output compare unit 7 75 2d0 reserved 76 2cc reserved 77 2c8 frt0 yes 77 free running timer 0 78 2c4 frt1 yes 78 free running timer 1 79 2c0 reserved 80 2bc reserved 81 2b8 rtc0 no 81 real timer clock 82 2b4 cal0 no 82 clock calibration unit 83 2b0 iic0 yes 83 i2c interface 84 2ac adc0 yes 84 a/d converter 85 2a8 linr2 yes 85 lin usart 2 rx 86 2a4 lint2 yes 86 lin usart 2 tx 87 2a0 linr3 yes 87 lin usart 3 rx 88 29c lint3 yes 88 lin usart 3 tx 89 298 linr7 yes 89 lin usart 7 rx 90 294 lint7 yes 90 lin usart 7 tx 91 290 linr8 yes 91 lin usart 8 rx 92 28c lint8 yes 92 lin usart 8 tx 93 288 flash_a no 93 flash memory a (only flash devices) interrupt vector table mb96(f)35x (3 / 3) vector number offset in vector ta- ble vector name cleared by dma index in icr to pro- gram description
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 53 handling devices special care is required for the following when handling the device: latch-up prevention unused pins handling external clock usage unused sub clock signal notes on pll clock mode operation power supply pins (v cc /v ss ) crystal oscillator circuit turn on sequence of power supply to a/d converter and analog inputs pin handling when not using the a/d converter notes on energization stabilization of power supply voltage 1. latch-up prevention cmos ic chips may suffer latch-up under the following conditions: a voltage higher than v cc or lower than v ss is applied to an input or output pin. a voltage higher than the rated voltage is applied between v cc and v ss . latch-up may increase the power supply current dramatically, causing thermal damages to the device. 2. unused pins handling unused input pins can be left open when the input is disabled (corresponding bit of port input enable register pier = 0). leaving unused input pins open when the input is enabled may result in misbehavior and possible permanent damage of the device. they must therefore be pulled up or pulled down through resistors. to prevent latch- up, those resistors should be more than 2 k ? . unused bidirectional pins can be set either to the output state and be then left open, or to the input state with either input disabled or external pull-up/pull-down resistor as described above. 3. external clock usage the permitted frequency range of an external clock depends on the oscillator type and configuration. see ac characteristics for detailed modes and frequency limits. single and opposite phase external clocks must be connected as follows: 1. single phase external clock when using a single phase external clock, x0 pin must be driven and x1 pin left open. 2. opposite phase external clock when using an opposite phase external clock, x1 (x1a) must be supplied with a clock signal which has the x0 x1
preliminary mb96350 series fme-mb96350 rev 5 54 2008-2-4 opposite phase to the x0 (x0a) pins. 4. unused sub clock signal if the pins x0a and x1a are not connected to an oscillator, a pull-down resistor must be connected on the x0a pin and the x1a pin must be left open. 5. notes on pll clock mode operation if the pll clock mode is selected and no external oscillator is operating or no external clock is supplied, the microcontroller attempts to work with the free oscillating pll. performance of this operation, however, cannot be guaranteed. 6. power supply pins (v cc / v ss ) it is required that all v cc -level as well as all v ss -level power supply pins are at the same potential. if there is more than one v cc or v ss level, the device may operate incorrectly or be damaged even within the guaranteed operating range. ? cc and v ss must be connected to the device from the power supply with lowest possible impedance. as a measure against power supply noise, it is required to connect a bypass capacitor of about 0.1 f between v cc and v ss as close as possible to v cc and v ss pins. 7. crystal oscillator circuit noise at x0 or x1 pins might cause abnormal operation. it is required to provide bypass capacitors with shortest possible distance to x0, x1 pins, crystal oscillator (or ceramic resonator) and ground lines, and, to the utmost effort, that the lines of oscillation circuit do not cross the lines of other circuits. it is highly recommended to provide a printed circuit board art work surrounding x0 and x1 pins with a ground area for stabilizing the operation. it is highly recommended to evaluate the quartz/mcu system at the quartz manufacturer. 8. turn on sequence of power supply to a/d converter and analog inputs it is required to turn the a/d converter power supply (av cc , avrh, avrl) and analog inputs (ann) on after turning the digital power supply (v cc ) on. it is also required to turn the digital power off after turning the a/d converter supply and analog inputs off. in this case, the voltage must not exceed avrh or av cc (turning the analog and digital power supplies simultaneously on or off is acceptable). 9. pin handling when not using the a/d converter it is required to connect the unused pins of the a/d converter as av cc = v cc , av ss = avrh = avrl = v ss . 10. notes on energization to prevent malfunction of the internal voltage regulator, supply voltage profile while turning the power supply on should be slower than 50 s from 0.2 v to 2.7 v. 11. stabilization of power supply voltage x0 x1
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 55 if the power supply voltage varies acutely even within the operation safety range of the vcc power supply voltage, a malfunction may occur. the vcc power supply voltage must therefore be stabilized. as stabilization guidelines, the power supply voltage must be stabilized in such a way that vcc ripple fluctuations (peak to peak value) in the commercial frequencies (50 to 60 hz) fall within 10% of the standard vcc power supply voltage and the transient fluctuation rate becomes 0.1v/ s or less in instantaneous fluctuation for power supply switching.
preliminary mb96350 series fme-mb96350 rev 5 56 2008-2-4
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 57 electrical characteristics 1. absolute maximum ratings warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. parameter symbol rating unit remarks min max power supply voltage v cc v ss - 0.3 v ss + 6.0 v av cc v ss - 0.3 v ss + 6.0 v v cc = av cc *1 ad converter voltage references avrh, avrl v ss - 0.3 v ss + 6.0 v av cc avrh, av cc avrl, avrh > avrl, avrl av ss input voltage v i v ss - 0.3 v ss + 6.0 v v i v cc + 0.3v *2 output voltage v o v ss - 0.3 v ss + 6.0 v v o v cc + 0.3v *2 maximum clamp current i clamp -4.0 +4.0 ma applicable to general purpose i/ o pins *3 total maximum clamp current |i clamp | - 40 ma applicable to general purpose i/ o pins *3 ??level maximum output current i ol1 - 15 ma normal outputs with driving strength set to 5ma ??level average output current i olav1 - 5 ma normal outputs with driving strength set to 5ma ??level maximum overall output current i ol1 - 100 ma normal outputs ??level average overall output current i olav1 - 50 ma normal outputs ??level maximum output current i oh1 - -15 ma normal outputs with driving strength set to 5ma ??level average output current i ohav1 - -5 ma normal outputs with driving strength set to 5ma ? level maximum overall output current i oh1 - -100 ma normal outputs ??level average overall output current i ohav1 - -50 ma normal outputs permitted power dissipation (flash de- vices) *4 p d - 320 *5 mw t a =105 o c - 640 *5 mw t a =85 o c - 800 *5 mw t a =75 o c - 400 *5 mw t a =125 o c, no flash program/ erase *6 - 560 *5 mw t a =115 o c, no flash program/ erase *6 operating ambient temperature t a 0 +70 o c mb96v300b -40 +105 -40 +125 *6
preliminary mb96350 series fme-mb96350 rev 5 58 2008-2-4 *1: av cc and v cc must be set to the same voltage. it is required that av cc does not exceed v cc and that the voltage at the analog inputs does not exceed av cc neither when the power is switched on. *2: v i and v o should not exceed v cc + 0.3 v. v i should also not exceed the speci?d ratings. however if the maximum current to/from a input is limited by some means with external components, the i clamp rating super- sedes the v i rating. input/output voltages of standard ports depend on v cc. *3: ? applicable to all general purpose i/o pins (pnn_m) ? use within recommended operating conditions. ? use at dc voltage (current) ? the +b signal should always be applied a limiting resistance placed between the +b signal and the microcontroller. ? the value of the limiting resistance should be set so that when the +b signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. ? note that when the microcontroller drive current is low, such as in the power saving modes, the +b input potential may pass through the protective diode and increase the potential at the vcc pin, and this may affect other devices. ? note that if a +b signal is input when the microcontroller power supply is off (not ?ed at 0 v), the power supply is provided from the pins, so that incomplete operation may result. ? note that if the +b input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be suf?ient to operate the power reset (except devices with persistent low voltage reset in internal vector mode). ? sample recommended circuits: *4: the maximum permitted power dissipation depends on the ambient temperature, the air ?w velocity and the thermal conductance of the package on the pcb. the actual power dissipation depends on the customer application and can be calculated as follows: p d = p io + p int p io = (v ol * i ol + v oh * i oh ) (io load power dissipation, sum is performed on all io ports) p int = v cc * (i cc + i a ) (internal power dissipation) i cc is the total core current consumption into v cc as described in the ?c characteristics and depends on the selected operation mode and clock frequency and the usage of functions like flash programming or the clock modulator. i a is the analog current consumption into av cc . storage temperature t stg -55 +150 o c parameter symbol rating unit remarks min max p-ch n-ch v cc r protective diode limiting resistance +b input (0v to 16v)
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 59 *5: worst case value for a package mounted on single layer pcb at speci?d t a without air ?w. *6: please contact fujitsu for reliability limitations when using under these conditions.
preliminary mb96350 series fme-mb96350 rev 5 60 2008-2-4
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 61 2. recommended conditions warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are guaranteed when the device is operated within these ranges. semiconductor devices must always be operated within their recommended operating condition ranges. oper- ation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu repre- sentatives beforehand. parameter symbol value unit remarks min typ max power supply voltage v cc 3.0 - 5.5 v smoothing capacitor at c pin c s 4.7 - 10 f use a low inductance capacitor (for example x7r ceramic ca- pacitor)
preliminary mb96350 series fme-mb96350 rev 5 62 2008-2-4
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 63 3. dc characteristics (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v, v ss = av ss = 0v) parameter symbol pin condition value unit remarks min typ max input ??voltage v ih port inputs pnn_m cmos hysteresis 0.8/0.2 input se- lected 0.8 v cc - v cc + 0.3 v cmos hysteresis 0.7/0.3 input se- lected 0.7 v cc - v cc + 0.3 vv cc 4.5v 0.74 v cc - v cc + 0.3 vv cc < 4.5v automotive hysteresis input selected 0.8 v cc - v cc + 0.3 v ttl input select- ed 2.0 - v cc + 0.3 v v ihx0f x0 external clock in ?ast clock input mode 0.8 v cc - v cc + 0.3 v v ihx0s x0,x1, x0a,x1a external clock in ?scillation mode 2.5 - v cc + 0.3 v v ihr rstx - 0.8 v cc - v cc + 0.3 v cmos hysteresis in- put v ihm md2-md0 - v cc - 0.3 - v cc + 0.3 v input ??voltage v il port inputs pnn_m cmos hysteresis 0.8/0.2 input se- lected v ss - 0.3 - 0.2 v cc v cmos hysteresis 0.7/0.3 input se- lected v ss - 0.3 - 0.3 v cc v automotive hysteresis input selected v ss - 0.3 - 0.5 v cc vv cc 4.5v v ss - 0.3 - 0.46 v cc v cc < 4.5v ttl input select- ed v ss - 0.3 - 0.8 v v ilx0f x0 external clock in ?ast clock input mode v ss - 0.3 - 0.2 v cc v v ilx0s x0,x1, x0a,x1a external clock in ?scillation mode v ss - 0.3 -0.5 v v ilr rstx - v ss - 0.3 - 0.2 v cc v cmos hysteresis in- put v ilm md2-md0 - v ss - 0.3 - v ss + 0.3 v
preliminary mb96350 series fme-mb96350 rev 5 64 2008-2-4 output ? voltage v oh2 normal outputs 4.5v v cc 5.5v i oh = -2ma v cc - 0.5 -- v driving strength set to 2ma 3.0v v cc < 4.5v i oh = -1.6ma v oh5 normal outputs 4.5v v cc 5.5v i oh = -5ma v cc - 0.5 -- v driving strength set to 5ma 3.0v v cc < 4.5v i oh = -3ma v oh3 i 2 c outputs 4.5v v cc 5.5v i oh = -3ma v cc - 0.5 -- v 3.0v v cc < 4.5v i oh = -2ma output ??voltage v ol2 normal outputs 4.5v v cc 5.5v i ol = +2ma - - 0.4 v driving strength set to 2ma 3.0v v cc < 4.5v i ol = +1.6ma v ol5 normal outputs 4.5v v cc 5.5v i ol = +5ma - - 0.4 v driving strength set to 5ma 3.0v v cc < 4.5v i ol = +3ma v ol3 i 2 c outputs 4.5v v cc 5.5v i ol = +3ma - - 0.4 v 3.0v v cc < 4.5v i ol = +2ma input leak current i il pnn_m v cc = 5.5v v ss < v i < v cc -1 - +1 a pull-up resistance r up pnn_m, rstx - 25 50 100 k ? (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v, v ss = av ss = 0v) parameter symbol pin condition value unit remarks min typ max
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 65 (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v, v ss = av ss = 0v) parameter symbol condition value temp remarks typ max unit power supply cur- rent in run modes* i ccpll pll run mode with clks1/2 = 48mhz, clkb = clkp1/2 = 24mhz 35 44 ma 25?c clkrc and clksc stopped. core voltage at 1.9v 0 flash/rom wait states 36 47 125?c pll run mode with clks1/2 = clkb = clkp1= 56mhz, clkp2 = 28mhz 44 57 ma 25?c clkrc and clksc stopped. core voltage at 1.9v 2 flash/rom wait states 45 60 125?c pll run mode with clks1/2 = 96mhz, clkb = clkp1= 48mhz, clkp2 = 24mhz 49 62 ma 25?c clkrc and clksc stopped. core voltage at 1.9v 1 flash/rom wait state 50 65 125?c i ccmain main run mode with clks1/2 = clkb = clkp1/2 = 4mhz 4.5 5.5 ma 25?c clkpll, clksc and clkrc stopped 1 flash/rom wait state 5.1 8.5 125?c i ccrch rc run mode with clks1/2 = clkb = clkp1/2 = 2mhz 2.9 4 ma 25?c clkmc, clkpll and clksc stopped 1 flash/rom wait state 3.5 6.5 125?c
preliminary mb96350 series fme-mb96350 rev 5 66 2008-2-4 power supply cur- rent in run modes* i ccrcl rc run mode with clks1/2 = clkb = clkp1/2 = 100khz, smcr:lpms = 0 0.4 0.6 ma 25?c clkmc, clkpll and clksc stopped. volt- age regulator in high power mode 1 flash/rom wait state 0.9 3.5 125?c rc run mode with clks1/2 = clkb = clkp1/2 = 100khz, smcr:lpms = 1 0.15 0.25 ma 25?c clkmc, clkpll and clksc stopped. volt- age regulator in low pow- er mode, no flash pro- gramming/erasing allowed. 1 flash/rom wait state 0.65 3.2 125?c i ccsub sub run mode with clks1/2 = clkb = clkp1/2 = 32khz 0.1 0.2 ma 25?c clkmc, clkpll and clkrc stopped, no flash programming/ erasing allowed. 1 flash/rom wait state 0.6 3 125?c (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v, v ss = av ss = 0v) parameter symbol condition value temp remarks typ max unit
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 67 power supply cur- rent in sleep modes* i ccspll pll sleep mode with clks1/2 = 48mhz, clkp1/2 = 24mhz 9 10.5 ma 25?c clkrc and clksc stopped. core voltage at 1.9v 9.7 13 125?c pll sleep mode with clks1/2 = clkp1= 56mhz, clkp2 = 28mhz 14 15.5 ma 25?c clkrc and clksc stopped. core voltage at 1.9v 14.8 18 125?c pll sleep mode with clks1/2 = 96mhz, clkp1= 48mhz, clkp2 = 24mhz 14 15.5 ma 25?c clkrc and clksc stopped. core voltage at 1.9v 14.8 18 125?c i ccsmain main sleep mode with clks1/2 = clkp1/2 = 4mhz 1.5 1.8 ma 25?c clkpll, clksc and clkrc stopped 2 4.5 125?c i ccsrch rc sleep mode with clks1/2 = clkp1/2 = 2mhz 0.8 1.3 ma 25?c clkmc, clkpll and clksc stopped 1.4 4 125?c (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v, v ss = av ss = 0v) parameter symbol condition value temp remarks typ max unit
preliminary mb96350 series fme-mb96350 rev 5 68 2008-2-4 power supply cur- rent in sleep modes* i ccsrcl rc sleep mode with clks1/2 = clkp1/2 = 100khz, smcr:lpmss = 0 0.3 0.5 ma 25?c clkmc, clkpll and clksc stopped. volt- age regulator in high power mode 0.8 3.4 125?c rc sleep mode with clks1/2 = clkp1/2 = 100khz, smcr:lpmss = 1 0.06 0.15 ma 25?c clkmc, clkpll and clksc stopped. volt- age regulator in low pow- er mode 0.56 3 125?c i ccssub sub sleep mode with clks1/2 = clkp1/2 = 32khz 0.04 0.12 ma 25?c clkmc, clkpll and clkrc stopped 0.54 2.9 125?c (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v, v ss = av ss = 0v) parameter symbol condition value temp remarks typ max unit
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 69 power supply cur- rent in timer modes* i cctpll pll timer mode with clkmc = 4mhz, clk- pll = 48mhz 1.6 2 ma 25?c clkrc and clksc stopped. core voltage at 1.9v 2.1 4.8 125?c i cctmain main timer mode with clkmc = 4mhz, smcr:lpmss = 0 0.35 0.5 ma 25?c clkpll, clkrc and clksc stopped. volt- age regulator in high power mode 0.85 3.3 125?c main timer mode with clkmc = 4mhz, smcr:lpmss = 1 0.1 0.15 ma 25?c clkpll, clkrc and clksc stopped. volt- age regulator in low pow- er mode 0.6 2.9 125?c i cctrch rc timer mode with clkrc = 2mhz, smcr:lpmss = 0 0.35 0.5 ma 25?c clkmc, clkpll and clksc stopped. volt- age regulator in high power mode 0.85 3.3 125?c rc timer mode with clkrc = 2mhz, smcr:lpmss = 1 0.1 0.15 ma 25?c clkmc, clkpll and clksc stopped. volt- age regulator in low pow- er mode 0.6 2.9 125?c i cctrcl rc timer mode with clkrc = 100khz, smcr:lpmss = 0 0.3 0.45 ma 25?c clkmc, clkpll and clksc stopped. volt- age regulator in high power mode 0.8 3.2 125?c rc timer mode with clkrc = 100khz, smcr:lpmss = 1 0.05 0.1 ma 25?c clkmc, clkpll and clksc stopped. volt- age regulator in low pow- er mode 0.55 2.8 125?c (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v, v ss = av ss = 0v) parameter symbol condition value temp remarks typ max unit
preliminary mb96350 series fme-mb96350 rev 5 70 2008-2-4 power supply cur- rent in timer modes* i cctsub sub timer mode with clksc = 32khz 0.03 0.1 ma 25?c clkmc, clkpll and clkrc stopped 0.53 2.8 125?c stop mode i cch vrcr:lpmb[2:0] = ?10 0.02 0.08 ma 25?c core voltage at 1.8v 0.52 2.8 125?c vrcr:lpmb[2:0] = ?00 0.015 0.06 ma 25?c core voltage at 1.2v 0.4 2.3 125?c power supply cur- rent for active low voltage detector i cclvd low voltage detector en- abled (rcr:lvde=?? 90 140 a 25?c this current must be added to all power sup- ply currents above 100 150 125?c clock modulator current i ccclomo clock modulator en- abled (cmcr:pdx = ?? 3 4.5 ma - must be added to all cur- rent above flash write/erase current i ccflash current for one flash module 15 40 ma - must be added to all cur- rent above input capacitance c in - 5 15 pf other than c, av cc , av ss , avrh, avrl, v cc , v ss * the power supply current is measured with a 4mhz external clock connected to the main oscillator and a 32khz external clock connected to the sub oscillator. see chapter ?tandby mode and voltage regulator control circuit of the hardware manual for further details about voltage regulator control. (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v, v ss = av ss = 0v) parameter symbol condition value temp remarks typ max unit
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 71 4. ac characteristics source clock timing (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v, v ss = av ss = 0v) parameter symbol pin value unit remarks min typ max clock frequency f c x0, x1 3 - 16 mhz when using an oscillation circuit, pll off 0 - 16 mhz when using an opposite phase external clock, pll off 3.5 - 16 mhz when using an oscillation circuit or op- posite phase external clock, pll on clock frequency f fci x0 0 - 56 mhz when using a single phase external clock in fast clock input mode , pll off 3.5 - 56 mhz when using a single phase external clock in fast clock input mode , pll on clock frequency f cl x0a, x1a 32 32.768 100 khz when using an oscillation circuit 0 - 100 khz when using an opposite phase external clock x0a 0 - 50 khz when using a single phase external clock clock frequency f cr - 50 100 200 khz when using slow frequency of rc oscil- lator 1 2 4 mhz when using fast frequency of rc oscil- lator clock frequency f clkvco - 50 - 200 mhz permitted vco output frequency of pll (clkvco) input clock pulse width p wh , p wl x0,x1 8 - - ns duty ratio is about 30% to 70% input clock pulse width p whl , p wll x0a,x1a 5 - - s
preliminary mb96350 series fme-mb96350 rev 5 72 2008-2-4 x0 t cyl p wh p wl v il v ih x0a t cyll p whl p wll v il v ih
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 73 internal clock timing (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v, v ss = av ss = 0v) parameter symbol core voltage settings unit remarks 1.8v 1.9v min max min max internal system clock fre- quency (clks1 and clks2) f clks1 , f clks2 0 92 0 96 mhz others than below 0 88 0 96 mhz mb96f356 internal cpu clock fre- quency (clkb), internal peripheral clock frequency (clkp1) f clkb , f clkp1 052056mhz internal peripheral clock frequency (clkp2) f clkp2 028032mhz
preliminary mb96350 series fme-mb96350 rev 5 74 2008-2-4
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 75 external reset timing (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v, v ss = av ss = 0v) parameter symbol pin value unit remarks min typ max reset input time t rstl rstx 500 - - ns 0.2 v cc rstx t rstl 0.2 v cc
preliminary mb96350 series fme-mb96350 rev 5 76 2008-2-4
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 77 power on reset timing (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v, v ss = av ss = 0v) parameter symbol pin value unit remarks min typ max power on rise time t r vcc 0.05 - 30 ms power off time t off vcc 1 - - ms 0.2 v t r 2.7v t off 0.2 v 0.2 v if the power supply is changed too rapidly, a power-on reset may occur. we recommend a smooth startup by restraining voltages when changing the power supply voltage during operation, as shown in the ?ure below. 3 v v cc v cc rising edge of 50 mv/ms maximum is allowed
preliminary mb96350 series fme-mb96350 rev 5 78 2008-2-4
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 79 external input timing note : relocated resource inputs have same characteristics (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v, v ss = av ss = 0v) parameter symbol pin condition value unit used pin input func- tion min max input pulse width t inh t inl intn ? 200 ? ns external interrupt nmi nmi pnn_m 2*t clkp1 + 200 (t clkp1 =1/ f clkp1 ) ? ns general purpose io tinn reload timer ttgn ppg trigger input adtg ad converter trigger frckn free running timer external clock inn input capture v il v ih t inh v il v ih t inl external pin input
preliminary mb96350 series fme-mb96350 rev 5 80 2008-2-4
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 81 external bus timing warning: the values given below are for an i/o driving strength io drive =5ma.ifio drive is 2ma, all the maximum output timing described in the different tables must then be increased by 10ns. basic timing ( t a =? 40 c to + 125 c, v cc = 5.0 v 10 % , v ss = 0.0 v, io drive = 5ma, c l = 50pf) parameter symbol pin condition value unit remarks min max eclk t cyc eclk ? 25 ? ns t chcl t cyc /2-5 t cyc /2+5 t clch t cyc /2-5 t cyc /2+5 eclk ubx/ lbx / csn time t chcbh csn, ubx, lbx, eclk ? -20 20 ns t chcbl -20 20 t clcbh -20 20 t clcbl -20 20 eclk ale time t chlh ale, eclk ? -10 10 ns t chll -10 10 t cllh -10 10 t clll -10 10 eclk address valid time t chav a[23:16], eclk ? -15 15 ns t clav -15 15 t cladv ad[15:0], eclk ? -15 15 ns t chadv -15 15 eclk rdx /wrx time t chrwh rdx, wrx, wrlx,wrhx, eclk ? -10 10 ns t chrwl -10 10 t clrwh -10 10 t clrwl -10 10 ( t a =? 40 c to + 125 c, v cc = 3.0 to 4.5v , v ss = 0.0 v, io drive = 5ma, c l = 50pf) parameter symbol pin condition value unit remarks min max eclk t cyc eclk ? 30 ? ns t chcl t cyc /2-8 t cyc /2+8 t clch t cyc /2-8 t cyc /2+8 eclk ubx/ lbx / csn time t chcbh csn, ubx, lbx, eclk ? -25 25 ns t chcbl -25 25 t clcbh -25 25 t clcbl -25 25
preliminary mb96350 series fme-mb96350 rev 5 82 2008-2-4 refer to the hardware manual for detailed timing charts. eclk ale time t chlh ale, eclk ? -15 15 ns t chll -15 15 t cllh -15 15 t clll -15 15 eclk address valid time t chav a[23:16], eclk ? -20 20 ns t clav -20 20 t cladv ad[15:0], eclk ? -20 20 ns t chadv -20 20 eclk rdx /wrx time t chrwh rdx, wrx, wrlx, wrhx, eclk ? -15 15 ns t chrwl -15 15 t clrwh -15 15 t clrwl -15 15 ( t a =? 40 c to + 125 c, v cc = 3.0 to 4.5v , v ss = 0.0 v, io drive = 5ma, c l = 50pf) parameter symbol pin condition value unit remarks min max eclk t cyc csn ale a[23:16] 0.2*vcc t chcl t chav t chcbl t chcbh lbx ubx t cllh t chll t chlh t clll t cladv ad[15:0] address t clav t chadv t clcbh t clcbl t chrwh t clrwh t clrwl t chrwl rdx wrx (wrlx, wrhx) 0.8*vcc t clch
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 83 bus timing (read) (t a =? 40 c to + 125 c, v cc = 5.0 v 10 % , v ss = 0.0 v, io drive = 5ma, c l = 50pf) parameter sym- bol pin conditions value unit remarks min max ale pulse width t lhll ale eacl:sts=0 and eacl:ace=0 t cyc /2 ? 5 ? ns eacl:sts=1 t cyc ? 5 ? eacl:sts=0 and eacl:ace=1 3t cyc /2 ? 5 ? valid address ? ale time t avll ale, a[23:16], eacl:sts=0 and eacl:ace=0 t cyc ? 15 ? ns eacl:sts=1 and eacl:ace=0 3t cyc /2 ? 15 ? eacl:sts=0 and eacl:ace=1 2t cyc ? 15 ? eacl:sts=1 and eacl:ace=1 5t cyc /2 ? 15 ? t advll ale,ad[15:0] eacl:sts=0 and eacl:ace=0 t cyc /2 ? 15 ? ns eacl:sts=1 and eacl:ace=0 t cyc ? 15 ? eacl:sts=0 and eacl:ace=1 3t cyc /2 ? 15 ? eacl:sts=1 and eacl:ace=1 2t cyc ? 15 ? ale ? address valid time t llax ale, ad[15:0] eacl:sts=0 t cyc /2 ? 15 ? ns eacl:sts=1 -15 ? valid address ? rdx time t avrl rdx, a[23:16] eacl:ace=0 3t cyc /2 ? 15 ? ns eacl:ace=1 5t cyc /2 ? 15 ? t advrl rdx, ad[15:0] eacl:ace=0 t cyc ? 15 ? ns eacl:ace=1 2t cyc ? 15 ? valid address ? valid data input t avdv a[23:16], ad[15:0] eacl:ace=0 ? 3t cyc ? 55 ns w/o cycle extension eacl:ace=1 ? 4t cyc ? 55 t advdv ad[15:0] eacl:ace=0 ? 5t cyc /2 ? 55 ns w/o cycle extension eacl:ace=1 ? 7t cyc /2 ? 55 rdx pulse width t rlrh rdx ? 3 t cyc /2 ? 5 ? ns w/o cycle extension rdx ? valid data input t rldv rdx, ad[15:0] ?? 3t cyc /2 ? 50 ns w/o cycle extension rdx ? data hold time t rhdx rdx, ad[15:0] ? 0 ? ns
preliminary mb96350 series fme-mb96350 rev 5 84 2008-2-4 address valid ? data hold time t axdx a[23:16], ad[15:0] ? 0 ? ns rdx ? ale time t rhlh rdx, ale eacl:sts=1 and eacl:ace=1 3t cyc /2 ? 10 ? ns other ecl:sts, eacl:ace setting t cyc /2 ? 10 ? valid address ? eclk time t avch a[23:16], eclk ? t cyc ? 15 ? ns t advch ad[15:0], eclk t cyc /2 ? 15 ? rdx ? eclk time t rlch rdx, clk ? t cyc /2 ? 10 ? ns ale ? rdx time t llrl ale, rdx eacl:sts=0 t cyc /2 ? 10 ? ns eacl:sts=1 ? 10 ? eclk ? valid data input t chdv ad[15:0], eclk ?? t cyc ? 50 ns (t a =? 40 c to + 125 c, v cc = 3.0 to 4.5v , v ss = 0.0 v, io drive = 5ma, c l = 50pf) parameter sym- bol pin conditions value unit remarks min max ale pulse width t lhll ale eacl:sts=0 and eacl:ace=0 t cyc /2 ? 8 ? ns eacl:sts=1 t cyc ? 8 ? eacl:sts=0 and eacl:ace=1 3t cyc /2 ? 8 ? valid address ? ale time t avll ale, a[23:16], eacl:sts=0 and eacl:ace=0 t cyc ? 20 ? ns eacl:sts=1 and eacl:ace=0 3t cyc /2 ? 20 ? eacl:sts=0 and eacl:ace=1 2t cyc ? 20 ? eacl:sts=1 and eacl:ace=1 5t cyc /2 ? 20 ? t advll ale, ad[15:0] eacl:sts=0 and eacl:ace=0 t cyc /2 ? 20 ? ns eacl:sts=1 and eacl:ace=0 t cyc ? 20 ? eacl:sts=0 and eacl:ace=1 3t cyc /2 ? 20 ? eacl:sts=1 and eacl:ace=1 2t cyc ? 20 ? ale ? address valid time t llax ale, ad[15:0] eacl:sts=0 t cyc /2 ? 20 ? ns eacl:sts=1 -20 ? (t a =? 40 c to + 125 c, v cc = 5.0 v 10 % , v ss = 0.0 v, io drive = 5ma, c l = 50pf) parameter sym- bol pin conditions value unit remarks min max
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 85 valid address ? rdx time t avrl rdx, a[23:16] eacl:ace=0 3t cyc /2 ? 20 ? ns eacl:ace=1 5t cyc /2 ? 20 ? t advrl rdx, ad[15:0] eacl:ace=0 t cyc ? 20 ? ns eacl:ace=1 2t cyc ? 20 ? valid address ? valid data input t avdv a[23:16], ad[15:0] eacl:ace=0 ? 3t cyc ? 60 ns w/o cycle extension eacl:ace=1 ? 4t cyc ? 60 t advdv ad[15:0] eacl:ace=0 ? 5t cyc /2 ? 60 ns w/o cycle extension eacl:ace=1 ? 7t cyc /2 ? 60 rdx pulse width t rlrh rdx ? 3t cyc /2 ? 8 ? ns w/o cycle extension rdx ? valid data input t rldv rdx, ad[15:0] ?? 3t cyc /2 ? 55 ns w/o cycle extension rdx ? data hold time t rhdx rdx, ad[15:0] ? 0 ? ns address valid ? data hold time t axdx a[23:16] ? 0 ? ns rdx ? ale time t rhlh rdx, ale eacl:sts=1 and eacl:ace=1 3t cyc /2 ? 15 ? ns other ecl:sts, eacl:ace setting t cyc /2 ? 15 ? valid address ? eclk time t avch a[23:16], eclk ? t cyc ? 20 ? ns t advch ad[15:0], eclk t cyc /2 ? 20 ? rdx ? eclk time t rlch rdx, clk ? t cyc /2 ? 15 ? ns ale ? rdx time t llrl ale, rdx eacl:sts=0 t cyc /2 ? 15 ? ns eacl:sts=1 ? 15 ? eclk ? valid data input t chdv ad[15:0], eclk ?? t cyc ? 55 ns (t a =? 40 c to + 125 c, v cc = 3.0 to 4.5v , v ss = 0.0 v, io drive = 5ma, c l = 50pf) parameter sym- bol pin conditions value unit remarks min max
preliminary mb96350 series fme-mb96350 rev 5 86 2008-2-4 refer to the hardware manual for detailed timing charts. bus timing (write) ( t a =? 40 c to + 125 c, v cc = 5.0 v 10 % , v ss = 0.0 v , io drive = 5ma, c l = 50pf ) parameter symbol pin condition value unit remarks min max valid address ? wrx time t avwl wrx, wrlx, wrhx, a[23:16] eacl:ace=0 3t cyc /2 ? 15 ? ns eacl:ace=1 5t cyc /2 ? 15 ? t advwl wrx, wrlx, wrhx, ad[15:0] eacl:ace=0 t cyc ? 15 ns eacl:ace=1 2t cyc ? 15 wrx pulse width t wlwh wrx, wrxl, wrhx ? t cyc ? 5 ? ns w/o cycle extension valid data output ? wrx time t dvwh wrx, wrlx, wrhx, ad[15:0] ? t cyc ? 20 ? ns w/o cycle extension a[23:16] ad[15:0] address v il v ih v ih v il read data t rhdx t rldv t advdv eclk t advch 0.8*vcc t rlch ale t lhll t rhlh 0.2*v cc t llax t advll rdx t llrl t rlrh t advrl t avch t avll t avdv t avrl t chdv t axdx
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 87 (t a =? 40 c to + 125 c, v cc = 3.0 to 4.5v, v ss = 0.0 v, io drive = 5ma, c l = 50pf) wrx ? data hold time t whdx wrx, wrlx, wrhx, ad[15:0] ? t cyc /2 ? 15 ? ns wrx ? address valid time t whax wrx, wrlx, wrhx, a[23:16] ? t cyc /2 ? 15 ? ns wrx ? ale time t whlh wrx, wrlx, wrhx, ale ebm:ace=1 and eacl:sts=1 2t cyc ? 10 ? ns other ebm:ace and eacl:sts setting t cyc ? 10 ? wrx ? eclk time t wlch wrx, wrlx, wrhx, eclk ? t cyc /2 ? 10 ? ns csn ? wrx time t cslwl wrx, wrlx, wrhx, csn eacl:ace=0 ? 3t cyc /2 ? 15 ns eacl:ace=1 ? 5t cyc /2 ? 15 wrx ? csn time t whcsh wrx, wrlx, wrhx, csn ? t cyc /2 ? 15 ? ns parameter symbol pin condition value unit remarks min max valid address ? wrx time t avwl wrx, wrlx, wrhx, a[23:16] eacl:ace=0 3t cyc /2 ? 20 ? ns eacl:ace=1 5t cyc /2 ? 20 ? t advwl wrx, wrlx, wrhx, ad[15:0] eacl:ace=0 t cyc ? 20 ns eacl:ace=1 2t cyc ? 20 wrx pulse width t wlwh wrx, wrxl, wrhx ? t cyc ? 8 ? ns w/o cycle extension valid data output ? wrx time t dvwh wrx, wrlx, wrhx, ad[15:0] ? t cyc ? 25 ? ns w/o cycle extension wrx ? data hold time t whdx wrx, wrlx, wrhx, ad[15:0] ? t cyc /2 ? 20 ? ns wrx ? address valid time t whax wrx, wrlx, wrhx, a[23:16] ? t cyc /2 ? 20 ? ns ( t a =? 40 c to + 125 c, v cc = 5.0 v 10 % , v ss = 0.0 v , io drive = 5ma, c l = 50pf ) parameter symbol pin condition value unit remarks min max
preliminary mb96350 series fme-mb96350 rev 5 88 2008-2-4 refer to the hardware manual for detailed timing charts. wrx ? ale time t whlh wrx, wrlx, wrhx, ale ebm:ace=1 and eacl:sts=1 2t cyc ? 15 ? ns other ebm:ace and eacl:sts setting t cyc ? 15 ? wrx ? eclk time t wlch wrx, wrlx, wrhx, eclk ? t cyc /2 ? 15 ? ns csn ? wrx time t cslwl wrx, wrlx, wrhx, csn eacl:ace=0 ? 3t cyc /2 ? 20 ns eacl:ace=1 ? 5t cyc /2 ? 20 wrx ? csn time t whcsh wrx, wrlx, wrhx, csn ? t cyc /2 ? 20 ? ns parameter symbol pin condition value unit remarks min max eclk t wlch 0.8*v cc ale t whlh wrx (wrlx, wrhx) t wlwh t advwl a[23:16] t whax ad[15:0] address write data t dvwh t whdx csn t whcsh t avwl t cslwl 0.2*v cc
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 89 ready input timing note : if the rdy setup time is insuf?ient, use the auto-ready function. refer to the hardware manual for detailed timing charts. hold timing ( t a =? 40 c to + 125 c, v cc = 5.0 v 10 % , v ss = 0.0 v , io drive = 5ma, c l = 50pf ) parameter symbol pin test condition rated value units remarks min max rdy setup time t ryhs rdy ? 35 ? ns rdy hold time t ryhh rdy 0 ? ns ( t a =? 40 c to + 125 c, v cc = 3.0 to 4.5v , v ss = 0.0 v , io drive = 5ma, c l = 50pf ) parameter symbol pin test condition rated value units remarks min max rdy setup time t ryhs rdy ? 45 ? ns rdy hold time t ryhh rdy 0 ? ns ( t a =? 40 c to + 125 c, v cc = 5.0 v 10 % , v ss = 0.0 v , io drive = 5ma, c l = 50pf ) parameter symbol pin condition value units remarks min max pin floating ? hakx time t xhal hakx ? t cyc ? 20 t cyc + 20 ns hakx time ? pin valid time t hahv hakx t cyc ? 20 t cyc +20 ns ( t a =? 40 c to + 125 c, v cc = 3.0 to 4.5v , v ss = 0.0 v , io drive = 5ma, c l = 50pf ) parameter symbol pin condition value units remarks min max pin floating ? hakx time t xhal hakx ? t cyc ? 25 t cyc +25 ns hakx time ? pin valid time t hahv hakx t cyc ? 25 t cyc +25 ns eclk rdy when wait is not used. v ih v ih t ryhh rdy when wait is used. t ryhs v il 0.8*v cc
preliminary mb96350 series fme-mb96350 rev 5 90 2008-2-4 refer to the h ardware manual for detailed timing charts. hakx each pin high-z t hahv t xhal 0.8*v cc 0.2*v cc 0.8*v cc 0.2*v cc
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 91 usart timing warning: the values given below are for an i/o driving strength io drive = 5ma. if io drive is 2ma, all the maximum output timing described in the different tables must then be increased by 10ns. notes: ? ac characteristic in clk synchronized mode. ? c l is the load capacity value of pins when testing. ? depending on the used machine clock frequency, the maximum possible baud rate can be limited by some parameters. these parameters are shown in ?b96300 super series hardware manual ? t clkp1 is the cycle time of the peripheral clock 1 (clkp1), unit : ns *1: parameter n depends on t scyci and can be calculated as follows: if t scyci = 2*k*t clkp1 , then n = k, where k is an integer > 2 if t scyci = (2*k+1)*t clkp1 , then n = k+1, where k is an integer > 1 examples: (t a = -40?c to 125?c, v cc = 3.0v to 5.5v, v ss = av ss = 0v, io drive = 5ma, c l = 50pf) parameter symbol pin condition v cc =av cc = 4.5v to 5.5v v cc =av cc = 3.0v to 4.5v unit min max min max serial clock cycle time t scyci sckn internal shift clock mode 4 t clkp1 ? 4 t clkp1 ? ns sck sot delay time t slovi sckn, sotn -20 + 20 -30 + 30 ns sot sck delay time t ovshi sckn, sotn n*t clkp1 - 20 *1 ? n*t clkp1 - 30 *1 ? valid sin sck t ivshi sckn, sinn t clkp1 + 45 ? t clkp1 + 55 ? ns sck valid sin hold time t shixi sckn, sinn 0 ? 0 ? ns serial clock ??pulse width t slshe sckn external shift clock mode t clkp1 + 10 ? t clkp1 + 10 ? ns serial clock ??pulse width t shsle sckn t clkp1 + 10 ? t clkp1 + 10 ? ns sck sot delay time t slove sckn, sotn ? 2 t clkp1 + 45 ? 2 t clkp1 + 55 ns valid sin sck t ivshe sckn, sinn t clkp1 /2 + 10 ? t clkp1 /2 + 10 ? ns sck valid sin hold time t shixe sckn, sinn t clkp1 + 10 ? t clkp1 + 10 ? ns sck fall time t fe sckn ? 20 ? 20 ns sck rise time t re sckn ? 20 ? 20 ns t scyci n 4*t clkp1 2 5*t clkp1, 6*t clkp1 3 7*t clkp1, 8*t clkp1 4 ... ...
preliminary mb96350 series fme-mb96350 rev 5 92 2008-2-4 internal shift clock mode sot t slovi sin v il v ih t ivshi v il v ih t shixi t ovshi sck for escr:sces = 0 0.8*v cc t scyci sck for escr:sces = 1 0.8*v cc 0.8*v cc 0.2*v cc 0.2*v cc 0.2*v cc 0.8*v cc 0.2*v cc external shift clock mode t fe v il v il v il v il sot t slove sin v il v ih t ivshe v il v ih t shixe v ih t re v ih t slshe v il v ih t shsle v ih v ih sck for escr:sces = 0 sck for escr:sces = 1 0.8*v cc 0.2*v cc
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 93 i 2 c timing *1 : r,c : pull-up resistor and load capacitor of the scl and sda lines. *2 : the maximum t hddat have only to be met if the device does not stretch the ??width (t low ) of the scl signal. *3 : a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement t sudat 250 ns must then be met. *4 : for use at over 100 khz, set the peripheral clock 1 to at least 6 mhz. (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v,v ss = av ss =0v) parameter symbol condition standard-mode fast-mode* 4 unit min max min max scl clock frequency f scl r = 1.7 k ? , c = 50 pf* 1 0 100 0 400 khz hold time (repeated) start condition sda scl t hdsta 4.0 ? 0.6 ? s ??width of the scl clock t low 4.7 ? 1.3 ? s ??width of the scl clock t high 4.0 ? 0.6 ? s set-up time for a repeated start condition scl sda t susta 4.7 ? 0.6 ? s data hold time scl sda t hddat 0 3.45* 2 0 0.9* 3 s data set-up time sda scl t sudat 250 ? 100 ? ns set-up time for stop condition scl sda t susto 4.0 ? 0.6 ? s bus free time between a stop and start condition t bus 4.7 ? 1.3 ? s sda scl t low t sudat t hdsta t bus t hdsta t hddat t high t susta t susto
preliminary mb96350 series fme-mb96350 rev 5 94 2008-2-4
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 95 5. analog digital converter note: the accuracy gets worse as |avrh - avrl| becomes smaller. de?ition of a/d converter terms resolution: analog variation that is recognized by an a/d converter. t otal error : difference between the actual value and the ideal value. the total error includes zero transition error, full-scale transition error and linear error. (t a = -40 ?c to +125 ?c, 3.0 v avrh - avrl, v cc = av cc = 3.0v to 5.5v, v ss = av ss = 0v) parameter symbol pin value unit remarks min typ max resolution - - - - 10 bit total error - - -3 - +3 lsb nonlinearity error - - -2.5 - +2.5 lsb differential nonlinearity error - - -1.9 - +1.9 lsb zero reading voltage v ot ann avrl - 1.5 avrl+ 0.5 avrl + 2.5 lsb full scale reading voltage v fst ann avrh - 3.5 avrh - 1.5 avrh + 0.5 lsb compare time - - 1.0 - 16,500 s 4.5v v cc 5.5v 2.0 - - s 3.0v v cc < 4.5v sampling time - - 0.5 - - s 4.5v v cc 5.5v 1.2 - - s 3.0v v cc < 4.5v analog port input cur- rent i ain ann -1 - +1 at a = 25 ?c -3 - +3 at a = 125 ?c analog input voltage range v ain ann avrl - avrh v reference voltage range avrh avrhav rh2 0.75 avcc - avcc v avrl avrl av ss - 0.25 av cc v power supply current i a avcc - 2.5 5 ma ad converter ac- tive i ah avcc - - 5 a ad converter not operated reference voltage cur- rent i r avrh/ avrl - 0.7 1 ma ad converter ac- tive i rh avrh/ avrl --5 a ad converter not operated offset between input channels - ann - - tbd lsb
preliminary mb96350 series fme-mb96350 rev 5 96 2008-2-4 non l inear ity error : deviation between a line across zero-transition line (?0 0000 0000 <--> ?0 0000 0001? and full-scale transition line (?1 1111 1110?<--> ?1 1111 1111? and actual conversion characteristics. diff erential linear ity error : deviation of input voltage, which is required for changing output code by 1 lsb, from an ideal value. z ero reading v oltage: input voltage which results in the minimum conversion value. full scale reading v oltage: input voltage which results in the maximum conversion value. 3ff 3fe 3fd 004 003 002 001 avrl avrh v nt 1.5 lsb 0.5 lsb {1 lsb (n ? 1) + 0.5 lsb} actual conversion characteristics (actually-measured value) actual conversion characteristics ideal characteristics digital output analog input total error of digital output ? = v nt ? {1 lsb (n ? 1) + 0.5 lsb} 1 lsb [lsb] 1 lsb = (ideal value) avrh ? avrl 1024 [v] v ot (ideal value) = avrl + 0.5 lsb [v] v fst (ideal value) = avrh ? 1.5 lsb [v] v nt : a voltage at which digital output transitions from (n ? 1) to n. total error n: a/d converter digital output value
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 97 notes on a/d converter section about the external impedance of the analog input and the sampling time of the a/d converter (with sample and hold circuit): if the external impedance is too high to keep suf?ient sampling time, the analog voltage charged to the internal sample and hold capacitor is insuf?ient, adversely affecting a/d conversion precision. 3ff 3fe 3fd 004 003 002 001 avrl avrh avrl avrh n + 1 n n ? 1 n ? 2 v ot ( actual measurement value ) {1 lsb (n ? 1) + v ot } actual conversion characteristics v fst (actual measurement value) v nt (actual measurement value) actual conversion characteristics ideal characteristics actual conversion characteristics actual conversion characteristics ideal characteristics digital output digital output analog input analog input v nt (actual measurement value) v (n + 1) t (actual measurement value) non linearity error differential linearity error differential linearity error of digital output n = 1 lsb = analog input circuit model: comparator sampling switch r c analog input reference value: c = 8.5 pf (max) non linearity error of digital output n = v nt ? {1 lsb (n ? 1) + v ot } 1 lsb [lsb] v ( n+1 ) t ? v nt 1 lsb ? 1 lsb [lsb] v fst ? v ot 1022 [v] n : a/d converter digital output value v ot : voltage at which digital output transits from ?00 h ?to ?01 h . v fst : voltage at which digital output transits from ?fe h ?to ?ff h .
preliminary mb96350 series fme-mb96350 rev 5 98 2008-2-4 to satisfy the a/d conversion precision standard, the relationship between the external impedance and minimum sampling time must be considered and then either the resistor value and operating frequency must be adjusted or the external impedance must be decreased so that the sampling time (t samp ) is longer than the minimum value. usually, this value is set to 7 , where = rc. if the external input resistance (r ext ) connected to the analog input is included, the sampling time is expressed as follows: t samp [min] = 7 (r ext + 2.6k ? ) c for 4.5 av cc 5.5 t samp [min] = 7 (r ext + 12.1k ? ) c for 3.0 av cc 4.5 if the sampling time cannot be suf?ient, connect a capacitor of about 0.1 f to the analog input pin. about the error the accuracy gets worse as |avrh - avrl| becomes smaller.
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 99 7. low voltage detector characteristics levels 10 to 15 are not used in this device. for correct detection, the slope of the voltage level must satisfy . faster variations are regarded as noise and may not be detected. the functional operation of the mcu is guaranteed down to the minimum low voltage detection level of vcc = 2.7v. the electrical characteristics however are only valid in the speci?d range (usually down to 3.0v). (t a = -40 ?c to +125 ?c, v cc = av cc = 3.0v - 5.5v, v ss = av ss = 0v) parameter symbol value unit remarks min max stabilization time t lvdstab 60 75 s level 0 v dl0 2.7 2.9 v cilcr:lvl[3:0]=?000 level 1 v dl1 2.9 3.1 v cilcr:lvl[3:0]=?001 level 2 v dl2 3.1 3.3 v cilcr:lvl[3:0]=?010 level 3 v dl3 3.5 3.75 v cilcr:lvl[3:0]=?011 level 4 v dl4 3.6 3.85 v cilcr:lvl[3:0]=?100 level 5 v dl5 3.7 3.95 v cilcr:lvl[3:0]=?101 level 6 v dl6 3.8 4.05 v cilcr:lvl[3:0]=?110 level 7 v dl7 3.9 4.15 v cilcr:lvl[3:0]=?111 level 8 v dl8 4.0 4.25 v cilcr:lvl[3:0]=?000 level 9 v dl9 4.1 4.35 v cilcr:lvl[3:0]=?001 level 10 v dl10 not used level 11 v dl11 not used level 12 v dl12 not used level 13 v dl13 not used level 14 v dl14 not used level 15 v dl15 not used t d d v 0.004 v s -----
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 100 low voltage detector operation in the following ?ure, the occurrence of a low voltage condition is illustrated. for a detailed description of the reset and startup behavior, please refer to the corresponding hardware manual chapter. voltage [v] time [s] v cc v dlx, min v dlx, max dv dt low voltage reset assertion normal operation power reset extension time
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 101 8. flash memory program/erase characteristics *1: this value was converted from the results of evaluating the reliability of the technology (using arrhenius equation to convert high temperature measurements into normalized value at 85 o c) ( t a = 25 o c , v cc = 5.0v) parameter value unit remarks min typ max sector erase time - 0.9 3.6 s erasure programming time not included chip erase time - n*0.9 n*3.6 s n is the number of flash sector of the device word (16-bit width) pro- gramming time - 23 370 us system overhead time not in- cluded programme/erase cycle 10 000 cycle flash data retention time 20 year *1
preliminary mb96350 series fme-mb96350 rev 5 102 2008-2-4
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 103 example characteristics the diagrams below show the characteristics of one measured sample with typical process parameters. run mode 0.01 0.10 1.00 10.00 100.00 -50.00 0.00 50.00 100.00 150.00 ta [?] icc [ma] main osc. (4 mhz) rc clock (2 mhz) rc clock (100 khz) sub osc.(32 khz) pll clock (56 mhz) sleep mode 0.01 0.10 1.00 10.00 100.00 -50.00 0.00 50.00 100.00 150.00 ta [?] icc [ma] main osc. (4 mhz) rc clock (100 khz) sub osc.(32 khz) rc clock (2 mhz) pll clock (56 mhz)
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 104 timer mode 0.01 0.10 1.00 10.00 -50.00 0.00 50.00 100.00 150.00 ta [?] icc [ma] main osc. (4 mhz) rc clock (100 khz) sub osc. (32 khz) pll clock (56 mhz) rc clock (2 mhz) stop mode 0.00 0.01 0.10 1.00 -50.00 0.00 50.00 100.00 150.00 ta [?] icc [ma]
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 105 used settings mode selected source clock clock/regulator settings run mode pll clks1 = clks2 = clkb = clkp1 = 56 mhz clkp2 = 28 mhz regulator in high power mode core voltage = 1.9 v main osc. clks1 = clks2 = clkb = clkp1 = clkp2 = 4 mhz regulator in high power mode core voltage = 1.8 v rc clock fast clks1 = clks2 = clkb = clkp1 = clkp2 = 2 mhz regulator in high power mode core voltage = 1.8 v rc clock slow clks1 = clks2 = clkb = clkp1 = clkp2 = 100 khz regulator in high power mode core voltage = 1.8 v sub osc. clks1 = clks2 = clkb = clkp1 = clkp2 = 32 khz regulator in low power mode a core voltage = 1.8 v sleep mode pll clks1 = clks2 = clkp1 = 56 mhz clkp2 = 28 mhz (clkb is stopped in this mode) regulator in high power mode core voltage = 1.9 v main osc. clks1 = clks2 = clkp1 = clkp2 = 4 mhz (clkb is stopped in this mode) regulator in high power mode core voltage = 1.8 v rc clock fast clks1 = clks2 = clkp1 = clkp2 = 2 mhz (clkb is stopped in this mode) regulator in high power mode core voltage = 1.8 v rc clock slow clks1 = clks2 = clkp1 = clkp2 = 100 khz (clkb is stopped in this mode) regulator in high power mode core voltage = 1.8 v sub osc. clks1 = clks2 = clkp1 = clkp2 = 32 khz (clkb is stopped in this mode) regulator in low power mode a core voltage = 1.8 v
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 106 timer mode pll clkmc = 4 mhz, clkpll = 56 mhz (system clocks are stopped in this mode) regulator in high power mode, core voltage = 1.9 v main osc. clkmc = 4 mhz (system clocks are stopped in this mode) regulator in high power mode, core voltage = 1.8 v rc clock fast clkrc = 2 mhz (system clocks are stopped in this mode) regulator in high power mode, core voltage = 1.8 v rc clock slow clkrc = 100 khz (system clocks are stopped in this mode) regulator in high power mode, core voltage = 1.8 v sub osc. clksc = 100 khz (system clocks are stopped in this mode) regulator in low power mode a, core voltage = 1.8 v stop mode stopped (all clocks are stopped in this mode) regulator in low power mode b, core voltage = 1.8 v used settings mode selected source clock clock/regulator settings
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 107 64-pin pl as tic lqfp le a d pitch 0.65 mm p a ck a ge width p a ck a ge length 12.0 12.0 mm le a d s h a pe g u llwing s e a ling method pl as tic mold mo u nting height 1.70 mm max code (reference) p-lfqfp64-12 12-0.65 64-pin pl as tic lqfp (fpt-64p-m2 3 ) (fpt-64p-m2 3 ) c 200 3 fujit s u limited f640 3 4 s -c-1-1 0.65(.026) 0.10(.004) 1 16 17 3 2 49 64 33 4 8 * 12.00?.10(.472?004) s q 14.00?.20(.551?00 8 ) s q index 0. 3 2?.05 (.01 3 ?002) m 0.1 3 (.005) 0.145?.055 (.0057?0022) "a" .059 ?004 +.00 8 ?.10 +0.20 1.50 0~ 8 ? 0.25(.010) (mo u nting height) 0.50?.20 (.020?00 8 ) 0.60?.15 (.024?006) 0.10?.10 (.004?004) det a il s of "a" p a rt ( s t a nd off) dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s note 1) * : the s e dimen s ion s do not incl u de re s in protr us ion. note 2) pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 3 )pin s width do not incl u de tie ba r c u tting rem a inder. package dimension mb96(f)35x lqfp 64 - m23
preliminary mb96350 series fme-mb96350 rev 5 108 2008-2-4 package dimension mb96(f)35x lqfp 64 - m24 64-pin plastic lqfp lead pitch 0.50 mm package width package length 10.0 10.0 mm lead shape gullwing sealing method plastic mold mounting height 1.70 mm max weight 0.32 g code (reference) p-lfqfp64-10 10-0.50 64-pin plastic lqfp (fpt-64p-m24) (fpt-64p-m24) lead no. details of "a" part 0.25(.010) (stand off) (.004.004) 0.100.10 (.024.006) 0.600.15 (.020.008) 0.500.20 1.50 +0.20 ?0.10 +.008 ?.004 .059 0 ? ~8 ? "a" 0.08(.003) (.006.002) 0.1450.055 0.08(.003) m (.008.002) 0.200.05 0.50(.020) 12.000.20(.472.008)sq 10.000.10(.394.004)sq index 49 64 33 48 17 32 16 1 2005 fujitsu limited f64036s-c-1-1 c (mounting height) * dimensions in mm (inches). note: the values in parentheses are reference values
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 109 ordering information this datasheet is also valid for the following outdated devices: mb96f356ysa, mb96f356rsa, mb96f356ywa, mb96f356rwa part number subclock persistent low volt- age reset package remarks mb96f356ysb pmc-gse2 no yes 64 pins plastic lqfp (fpt-64p-m23) mb96f356rsb pmc-gse2 no mb96f356ywb pmc-gse2 yes yes mb96f356rwb pmc-gse2 no mb96f356ysb pmc1-gse2 no yes 64 pins plastic lqfp (fpt-64p-m24) mb96f356rsb pmc1-gse2 no mb96f356ywb pmc1-gse2 yes yes mb96f356rwb pmc1-gse2 no mb96v300brb-es yes no 416 pin plastic bga (bga416-m02) for evalua- tion
preliminary mb96350 series fme-mb96350 rev 5 110 2008-2-4
preliminary mb96350 series fme-mb96350 rev 5 2008-2-4 111 revision history revision date modi?ation prelim 1 2007-05-03 creation prelim 2 2007-05-25 electrical characteristics update prelim 3 2007-11-27 package description is removed from cover page. typos corrections in product lineup. product option details added electrical characteristics update update of the block diagram update of the io map pin circuit type, lvd characteristics and example characteristics chapters added prelim 4 2007-12-20 update of the block diagram: external bus address lines, clock output function pins, avrl removed from adc block, relayout. ramstart value is corrected io map regenerated memory map and flash con?uration reworked few typos corrected accross the document. flash bank renaming. ordering information: package type corrected. io circuit drawings modi?d. prelim 5 2008-02-04 reload timer rlt 6 for ppgs added block diagram corrected: icu2 deleted, ttg2,3 deleted, ttg8,9 added pin function description corrected with all existing pin types i/o circuit type diagrams corrected memory map cleaned up "flash sector con?uration" replaced by corrected "user rom memory map for flash devices" parallel flash programming spec removed io map table regenerated: - port register: naming style corrected - memory control registers renamed (main -> a) - addresses after 000bffh removed handling devices: ad converter items added absolute maximum ratings: pd and ta speci?d more precisely run and sleep mode currents: more conditions added (1ws settings) run mode current spec in 48/24mhz mode corrected maximum clks1 frequency corrected at 1.8v external bus timings: missing conditions added and readability improved ordering information updated typos and formatting corrected
preliminary mb96350 series fme-mb96350 rev 5 112 2008-2-4
preliminary mb96350 series fme-mb96350 rev 5
preliminary mb96350 series fme-mb96350 rev 5 fujitsu limited all rights reserved. the contents of this document are subject to change without no- tice. customers are advised to consult with fujitsu sales repre- sentatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the pur- pose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper op- eration of the device with respect to use based on such informa- tion. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of func- tion and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of fujitsu or any third party or does fujitsu warrant non-infringement of any third-partys intellectual property right or other right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, per- sonal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support sys- tem, missile launch control in weapon system), or (2) for use re- quiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior au- thorization by japanese government will be required for export of those products from japan. the company names and brand names herein are the trademarks or registered trademarks of their respective owners.

▲Up To Search▲

Price & Availability of MB96F356YSBPMC-GSE2

	To Download MB96F356YSBPMC-GSE2 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .